
Fixed-Point DSP Processors
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Freescale 56F8xxx and DSP5685x (56800E)

The Freescale 56F8xxx and DSP5685x are two DSP families based on the 56800E core. The 56800E is a 16-bit fixed-point DSP architecture that uses 16-bit instructions. The 56800E is a slightly enhanced version of the 56800 core used in the DSP56F8xx family. The 56800E is assembly source-code upward compatible with the 56800. The DSP5685x targets automotive and motor control applications, as well as low-end cellular phones, PDAs, Internet audio, Internet/screen phones, and other Internet appliances. MC56F83xx chips are flash based, and target microcontroller applications that require modest DSP performance in fields such as automotive and industrial equipment.

There are 22 members in the 56F8xxx family. The 56F8xxx parts operate at up to 60 MHz at 2.5 volts. There are six members in the DSP5685x family. All operate at 120 MHz and 1.8 volts. All 56F8xxx and DSP5685x parts are currently shipping.

Architecture

The 56800E generally operates on 16-bit data; some 32- and 36-bit operations are also supported. The 56800E provides four 36-bit accumulator registers, each of which has four guard bits for overflow protection. Seven 16-bit data registers are available: four registers are composed of the 16 most significant bits in each accumulator, and three are independent 16-bit registers.

The data path of the 56800E is based on a 16 × 16 → 32-bit multiplier integrated with a 36-bit ALU and logic unit. Together with the logic unit, the multiplier-ALU combination (MAC unit) accepts up to three input operands and performs multiplications, additions, subtractions, logical operations, and other arithmetic operations to produce one 36-bit result. The MAC unit supports both integer and fractional multiplications. Operands may be signed/signed or signed/unsigned for fractional and integer multiplication; unsigned/unsigned multiplication is only supported for integers. The 56800E includes two shifters: a 36-bit accumulator shifter and a 32-bit barrel shifter. Bit manipulations on data memory words, peripheral registers, and all registers within the core are performed by a dedicated bit-manipulation unit that is capable of testing, setting, clearing, or inverting any bits specified in a 16-bit mask. The 56800E also has an exponent detector that can be used to compute the number of redundant sign bits in any of the seven data registers, allowing normalization of 16-bit values in two instruction cycles, and 32-bit values in three instruction cycles.

The 56800E employs a Harvard memory architecture that allows up to three simultaneous memory accesses: one instruction fetch plus two 16-bit data reads, one 32-bit data read, or one 32-bit data write. The total addressable program memory space is 4 Mbytes; the total addressable data memory address space is 32 Mbytes. On-chip memory includes separate program and data memories, each of which contains both RAM and ROM. When the processor is executing at 120 MHz, the maximum sustainable on-chip data memory bandwidth is 240 million 16-bit words/second for read operations or 240 million 16-bit words/second for write operations.

The 56800E supports memory-direct, register-direct, register-indirect, and modulo addressing modes. Immediate data is also supported. Bit-reversed addressing is not supported. The 56800E includes two hardware loop counters that support both single- and multi-instruction loops. Hardware loops are interruptible and may be nested.

Peripherals

Available peripherals on the DSP5685x family of devices include a Quad Timer module, two asynchronous serial ports (which Motorola calls “Serial Communications Interfaces”), up to two synchronous serial ports, a serial peripheral interface (SPI), a six-channel DMA controller, a Computer Operating Properly/Real-Time Interrupt (COP/RTI) module, and a time of day timer.

Available 56F83xx peripherals include some of the same peripherals as the DSP5685x family, including asynchronous serial ports, SPIs, a Quad Timer module, and COP/RTI module. Available 56F83xx peripherals also include 12-bit analog-to-digital converters, temperature sensors, quadrature decoders, and a FlexCAN module.

Power Consumption

The DSP56852 consumes about 120 mW at 120 MHz and 1.8 V when performing FIR filtering. This measurement includes the core, on-chip memory, the PLL, and on-chip peripherals. (The peripherals are clocked, but are not in active use.)

Cost

As of the last quarter of 2004, quantity 10,000 pricing for the 56F83xx ranged from $5.05 for the 56F8122 to $17.16 for the 56F8367. Quantity 10,000 pricing for the DSP5685x ranged from $3.59 for the DSP56852 to $6.80 for the DSP56858.

For Additional Information

The 56F8xx and DSP5685x achieve a BDTImark2000™ score of 340 at 120 MHz. For more information and scores, click here. A complete analysis of this processor, including BDTI Benchmark™ results, is contained in BDTI’s report, Buyer’s Guide to DSP Processors, 2004 Edition.

Last updated January 2005.

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