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Motorola DSP561xx Family

The Motorola DSP561xx family is based on Motorola's DSP56100 16-bit fixed-point DSP core and has an architecture, instruction set, and development environment similar to that of Motorola's DSP560xx 24-bit fixed-point processor family. DSP561xx processors execute at speeds up to 30 MIPS and are targeted at applications such as digital cellular telephones and pagers.

The two processors in the DSP561xx family are the DSP56156 (announced in late 1990) and the DSP56166 (announced in mid-1993). The former is aimed at the European GSM digital cellular market, while the latter targets U.S. IS-54 and Japanese digital cellular applications. Both offer on-chip voiceband A/D and D/A converters (codecs). The first member of the family, the DSP56116 (essentially a DSP56156 without the codec), was also announced in late 1990 but is no longer offered. Motorola does not plan to introduce new DSP561xx family members and is focusing its 16-bit product development on the DSP568xx and DSP566xx families.

The DSP561xx family's data path is based on a 16x16->32-bit multiplier integrated with a 40-bit accumulator, providing eight guard bits. Multiplier inputs can come from the X0, X1, Y0, and Y1 registers, as well as bits 16 through 31 of the two accumulators, A and B. Multiply-accumulate operations execute in a single cycle. The multiply-accumulate unit supports signed, signed/unsigned, and unsigned multiplication.

Although the data path does not include a barrel shifter, a shifting unit provides accumulator shifts of one or four bits left, or one, four, or 16 bits right. The data path supports both convergent and biased rounding as well as saturation and output shifting.

The DSP561xx family uses separate on-chip instruction (P) and data (X) memories. Both program and data memories are 16 bits wide and use 16-bit address buses. The program memory permits one instruction fetch per instruction cycle, while the data memory is dual-ported and supports two data reads or one read and one write per instruction cycle.

The DSP561xx's external data bus is made up of a 16-bit address bus and a 16-bit data bus. This bus set is multiplexed between program and data memories. Program/data, read, and write strobes indicate the type of bus cycle. One off-chip access can be made without penalty in a single instruction cycle, assuming no wait states. Each external access beyond one results in a one instruction cycle penalty.

DSP56156 on-chip peripherals include a sigma-delta codec (analog-to-digital and digital-to-analog), two serial ports, a host interface port, and a 16-bit timer. The DSP56166 features the same set of peripherals except that the DSP56156's serial ports are replaced by ``reduced'' serial ports that provide fewer features.

DSP561xx processors are noteworthy because they include a sigma-delta codec on-chip. The sigma-delta codec provides linear, analog I/O with 16-bit resolution over a bandwidth of approximately 4 kHz. Motorola states that the codec has a signal to noise-plus-distortion ratio of greater than 60 dB. The codec typically interfaces to the DSP with a sample rate higher than 8 kHz (usually 16 or 24 kHz); the DSP must perform decimation and interpolation filtering and compensate for the codec's frequency response. Application examples provided by Motorola use a fourth-order biquad filter for these tasks.

A consequence of implementing interpolation, decimation and filtering in software is that less DSP processing power is available for other tasks. This can be a disadvantage relative to codecs that perform more processing in hardware.

According to Motorola, May 1997 prices for the DSP561xx ranged from $24.20 to $27.87 in quantity 1,000.

For detailed information on the Motorola DSP56166 including benchmark results and analysis, contact BDTI.

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