Fixed-Point DSP Processors
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Fixed-Point DSP Processors |
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Lucent Technologies DSP16xxThe DSP16xx is a 16-bit fixed-point DSP processor family from Lucent Technologies. The DSP16xx is based on the DSP1600 fixed-point core, whose architecture is similar to that of Lucent's older DSP16/DSP16A processors. Lucent also offers a high-performance family, the DSP16xxx, which is based on the DSP16xx but has major enhancements. The fastest processors in the DSP16xx family execute at up to 120 MIPS with 3.0-volt nominal supply, and up to 90 MIPS with 5.0-volt nominal supply voltage. The first member of the DSP16xx family was the DSP1610, introduced in mid-1990. New members were quickly added to the family, including the high-end DSP1611, DSP1616, DSP1617, and DSP1618, and the low-end DSP1604 and DSP1605. In 1996, Lucent introduced the 120 MIPS DSP1620, the fastest member of the DSP16xx family. The DSP1618, DSP1620, and DSP1628 contain an on-chip error correction co-processor (ECCP) for use in Viterbi decoding. The low-end DSP160x processors are aimed at the tapeless answering machine market and feature an on-chip dynamic RAM interface. The DSP16xx data path, called the data arithmetic unit (DAU), is based on a 16x16->32-bit multiplier, a 36-bit ALU/shifter, and two 36-bit accumulators providing four guard bits for overflow protection. Both the multiplier and the ALU/shifter are capable of single-cycle execution. On all DSP16xx processors except the DSP160x and POMP15, a bit manipulation unit (BMU) integrated into the DAU provides support for 36-bit barrel shifting (arithmetic and logical), exponent detection (with or without simultaneous normalization) for block floating-point implementation, and bit-field insertion and extraction (e.g., for error control coding). The DAU also includes a 15-word instruction cache. The DSP16xx memory system uses a modified Harvard architecture with two separate address spaces, X and Y. Each address space has its own on-chip 16-bit data bus and 16-bit address bus. X is read-only memory used for instructions and fixed data, while Y memory is used for variable data. The on-chip memory of the DSP16xx consists of 1 to 32 Kwords of dual-port RAM and 2 to 48 Kwords of ''program/coefficient'' ROM, depending on the family variant. All data memory writes require two instruction cycles. The maximum sustainable on-chip data memory bandwidth for a 120 MIPS DSP1620 is 240 16-bit Mwords/second for reads (if instructions are executed from cache) and 60 16-bit Mwords/second for writes. DSP16xx processors feature one external memory interface, which provides one 16-bit data bus and one 16-bit address bus. These buses are multiplexed between on-chip X and Y memory buses, and thus, one external memory read can be made per instruction cycle. External memory writes take two instruction cycles. DSP16xx processors provide two address generation units: the X address arithmetic unit (XAAU) and the Y address arithmetic unit (YAAU). The XAAU and YAAU are different: the XAAU is mainly concerned with generating instruction addresses, while the YAAU is mainly concerned with generating data addresses. The DSP16xx supports short and long immediate data, and register-direct, paged memory-direct, and register-indirect addressing modes. The DSP16xx family supports hardware looping via the DO instruction, which is used to load the instruction cache with up to 15 program words. Once loaded, these instructions execute from cache and free the X bus to be used for data fetches. The on-chip peripherals for DSP16xx family members include serial ports, timers, a parallel I/O port, a bit I/O port (each bit can be independently set and toggled), A/D and D/A converters, a bit manipulation unit, and an error correction co-processor, depending on the variant. As of October 1998, quantity 10,000 prices for DSP16xx family members range from $5.00 to $75.00. A complete analysis of this processor, including BDTI Benchmark™ results, is contained in BDTI's report, Buyer's Guide to DSP Processors, 1999 Edition.
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