DSP Cores
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DSP Cores |
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Clarkspur Design CD245x CoreThe CD245x family from Clarkspur Design, Inc. consists of the CD2450 DSP core and the CD2455 and CD2457 chips. The CD2450, introduced in 1994, is the second-generation fixed-point DSP core from Clarkspur Design. The core is intended to be used as part of an application-specific integrated circuit (ASIC); ASIC designers customize the amount of memory and selection of surrounding peripherals. Like its predecessor, the CD2400, the CD2450 core is targeted primarily at low-cost applications and contains few DSP-specific features. It is capable of 50 MIPS (20 ns instruction cycle time) at 5.0 volts. The CD2455 and CD2457 chips were designed as examples of CD2450 usage, and each contains a slightly modified CD2450 core combined with several off-core function units. An unusual and powerful feature of the CD2450 is that it can be scaled to have a native data word size of 16 to 24 bits. This allows the ASIC designer to select the most appropriate data width for the application. The instruction rate decreases slightly and core size increases as the native data word size increases above 16 bits. The 24-bit version of the core is capable of 45 MIPS (22 ns instruction cycle time) at 5.0 volts. Some Clarkspur product literature refers to the 24-bit version of the CD2450 as the CD2460. The CD2450 data path consists of a 16x16->31-bit multiplier, a 32-bit ALU, and a 32-bit accumulator. The CD2450 multiplier is an improvement over that of the CD2400, which truncated multiplier results to 24 bits. The CD2450 provides a program memory space and a data memory space. The data memory space is divided into two banks to allow two simultaneous data fetches. Program memory uses 16-bit address and data buses that are connected to up to 64 Kwords of off-core RAM or ROM. Similarly, each of the two data memory banks can consist of up to 64 Kwords of memory. No memory is provided on-core. The CD2450 supports three simultaneous memory reads (one from program memory and two from data memory) per instruction cycle without the use of a cache. Note, however, that only one data write can be performed per instruction cycle. The program and data memory address buses are 16 bits wide. Since program memory can be used for data storage, the program memory data bus is as wide as the core's native data word size (16 to 24 bits) even though instruction words are always 16 bits long. Similarly, the data memory data buses are as wide as the native data word size of the core (16 to 24 bits). The CD2450 supports register-direct, immediate, short memory-direct, and register-indirect addressing. Support for hardware looping is not included. For a complete evaluation of this processor, including BDTI Benchmark™ results, contact BDTI.
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