DSP Cores
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DSP Cores |
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Clarkspur Design CD2400 CoreThe CD2400 is a licensable 16-bit fixed-point DSP core from Clarkspur Design, Inc. Introduced in 1989, it is targeted primarily at fax modem applications. The core is intended to be used as part of an application-specific integrated circuit (ASIC); ASIC designers customize the amount of memory and selection of surrounding peripherals. The CD2400 is rated at 17 MIPS (60 ns instruction cycle time), but core licensees have achieved speeds of up to 25 MIPS (40 ns instruction cycle time). One core licensee is Zilog, whose Z893xx family of DSP processors is based on a variation of the CD2400. Clarkspur's design philosophy for the CD2400 was to keep the processor simple in order to reduce its size and power consumption, and its architecture contains few DSP-specific features. Its successor, the CD2450, was released in 1994. The CD2400 data path consists of a 16x16->24-bit multiplier, a 24-bit ALU, and a 24-bit accumulator. Most fixed-point DSP processors produce a full-width multiplier result and provide accumulators and ALUs with data words wider than the multiplier's result size.The CD2400, in contrast, truncates the 32-bit result of a 16x16-bit multiplication to 24 bits, reducing precision. Guard bits are not supported. The CD2400 provides a program memory space and a data memory space. The data memory space is divided into two banks to allow two simultaneous data fetches. Each of the two data memory banks consists of 256 16-bit words of RAM. Data memory resides on-core and cannot be expanded off-core. Program memory uses 16-bit address and data buses that are connected to up to 64 Kwords of off-core RAM or ROM. No program memory is provided on-core. The CD2400 supports three simultaneous memory reads (one from program memory and two from data memory) per instruction cycle without the use of a cache. Note, however, that only one data write can be performed per instruction cycle. Writes to program memory are not supported. The CD2400 supports register-direct, immediate, memory-direct, and register-indirect addressing, as well as a short-form version of paged-direct addressing. Hardware looping is not included. For a complete evaluation of this processor, including BDTI Benchmark™ results, contact BDTI.
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