Infineon Carmel

The Infineon Carmel is a 16-bit fixed-point VLIW-based DSP processor core, introduced in March of 1998. The core is targeted at the wireless telecom market, xDSL, set-top boxes, and various Internet applications. Infineon offers Carmel as a licensable core, and will also use the core in Infineon-designed application-specific chips. According to Infineon, initial production devices based on Carmel are expected to sample in mid-2000, and will execute at 166 MHz using a 1.8-volt supply. Carmel-based development chips have been fabricated and execute at 96 MHz using a 2.5-volt supply.

Carmel supports a mixed-width 24/48-bit instruction set. Most instructions are available in both lengths, with the longer version supporting a wider range of addressing and register options. Two 24-bit instructions may be executed in parallel, with some restrictions. In addition, up to six instructions can be issued and executed in parallel via user-defined "configurable long instruction words," or "CLIWs." Hence, Carmel has two modes of VLIW-like operation: execution of two predefined instructions at a time, and execution of a user-defined CLIW instruction that contains up to six predefined instructions.

Carmel has two 16-bit fixed-point data paths, each of which contains an ALU and a 16x16-bit MAC unit. One of the data paths also contains an exponent unit and shifter. The exponent unit handles exponent detection and block floating-point. The shifter supports arithmetic and logical shifts to the left or right by 0-40 bits, and it also supports bit-manipulation operations such as bit-field insert and extract and rotate-through-carry. The two data paths share a common set of source and destination registers. Carmel provides a total of six 40-bit accumulators (each providing 8 guard bits) and twenty-six 16-bit addressing registers, of which sixteen can be used as general-purpose registers.

When two 24-bit instructions are executed in parallel, each of them must execute in a different data path. Hence, it is not possible, for example, to pair an instruction that uses the shifter with an instruction that uses the exponenet unit.

CLIW instructions consist of a 48-bit reference line and a 96-bit definition. The reference line is used for naming the CLIW instruction, specifying memory operands to be used by the CLIW instruction, and storing conditional-execution information. The definition contains up to six instructions that will be executed in parallel as a CLIW instruction. CLIW instructions are positional; the six instructions must be ordered as:

MAC | ALU/exponent/shifter | MAC | ALU | MOVE | MOVE.

Note that two of the instructions can only be moves to or from memory. The reference line is required each time the CLIW instruction is used; the definition is stored only once.

Each ALU can perform SIMD-style operations by treating values in accumulators as packed 16-bit data. Special instructions are available for division iteration and finding maxima and minima. A special maximum/minimum instruction designed for use in Viterbi decoding automatically updates a "back trace" register by shifting the result of the comparison (1 or 0) into the least-significant bit.

Carmel has three independent memory spaces: program, data, and I/O. The program memory space is organized as 8 Mwords of 48-bit memory. It is accessed using a 24-bit address bus and a 48-bit data bus, allowing the retrieval of one 48-bit instruction or two adjacent 24-bit instructions aligned on a 48-bit boundary in a single cycle. A small, separate memory bank is used for storing CLIW instructions. It is accessed using its own 10-bit address bus and 96-bit data bus. The processor core does not contain any memory; Carmel-based chips will feature varying amounts and configurations of on-chip memory.

The data memory space is divided into two regions for a total of 64 Kwords. It is accessed using four on-core data bus sets. Each set includes a 16-bit address bus and 16-bit data bus. The four data bus sets allow Carmel to perform up to four reads, three reads and one write, or two reads and two writes per instruction cycle. Hence, on a 96 MHz Carmel, the maximum on-chip data memory bandwidth is 384 million 16-bit words/second.

Carmel provides an external bus set referred to as the FPI bus. The width of the FPI address and data buses are configurable by the core licensee; the address bus can range from 24 to 32 bits in width, while the data bus can range from 16 to 64 bits. Once bus handshaking has been completed, one access can be made over the FPI bus per instruction cycle. For a Carmel core running at 96 MHz and using a 16-bit-wide FPI bus, this corresponds to a peak external memory bandwidth of 96 million 16-bit words/second.

Addressing modes supported by Carmel include register-direct, memory-direct, register-indirect, indexed, reverse-carry, and modulo addressing. Immediate data is also supported.

Carmel supports zero-overhead hardware looping through its "repeat" and "block repeat" instructions.

Carmel does not contain any on-core peripherals. In its own Carmel-based chips, Infineon will provide various configurations of peripherals. Infineon offers a selection of peripheral modules to Carmel licensees.