Floating-Point DSP Processors
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Floating-Point DSP Processors |
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Lucent Technologies DSP32xxThe Lucent Technologies DSP32xx family of processors is based on the earlier DSP32C , but adds features that specifically address the needs of multimedia applications on personal computer and workstation platforms. Introduced in 1991, the DSP3210 was the first member of the DSP32xx family. The DSP3210 executes at a maximum of 16.7 MIPS with a 66.67 MHz input clock. A second family member, the DSP3207, was introduced in 1993. The DSP3207 executes at a maximum of 20 MIPS with an 80 MHz input clock. Both processors use a 5.0-volt power supply. Lucent Technologies states that the DSP3207 and the DSP3210 will be phased out beginning in September of 1997, and is encouraging its customers to instead use the DSP32C. In addition to the synchronous serial port found on the DSP32C, the DSP3210 provides a bit I/O port and a timer on-chip. The DSP3207 omits the serial port, but otherwise provides the same peripherals as the DSP3210. Neither of the DSP32xx family members include the parallel I/O port found on the DSP32C. The DSP32xx is a 32-bit floating-point processor with 30-bit addresses. Like the DSP32C, the DSP32xx is centered around a floating-point data path (called the data arithmetic unit or DAU) and an integer data path/address generation unit (called the control arithmetic unit or CAU). However, the DSP32xx expands the CAU from 24 bits to 32 bits. The floating-point data path of the DSP32xx incorporates a 32x32->45-bit floating-point multiplier, a 40-bit adder, and four 40-bit accumulators. Unlike other floating-point DSPs, the DSP32xx floating-point data path is not capable of performing arithmetic on integer values. Instead, integer arithmetic is handled in the CAU. The DSP32xx uses a modified Von Neumann memory architecture with a single memory space and a single set of address and data buses. The memory space contains up to four physically separate memory banks: two 1Kx32 on-chip RAM banks, a 256x32 on-chip boot ROM, and an off-chip memory bank. Instructions and data can reside in any of these banks. Four accesses can be completed per instruction cycle if two successive memory accesses are not made to external memory or to the boot ROM. If a program attempts more accesses than are allowed, the processor automatically inserts conflict wait states. All internal and external memory is byte-addressable. Unlike the DSP32C, the DSP32xx supports either big-endian or little-endian byte ordering to increase compatibility with general-purpose microprocessors . The DSP32xx external memory interface is different from that of the DSP32C. It is oriented towards interfacing with the main system memory of a personal computer or workstation. Thus, the interface provides signals to support interfacing with dynamic memories and provides selectable addressing schemes compatible with either Intel or Motorola microprocessors. The DSP32xx provides a single 30-bit address, 32-bit data external memory interface with four byte-select/word size lines. The 30 bits of the address specify a 32-bit word, and the byte-select/word size lines specify the needed bytes within the 32-bit data word. Thus, the processor can address up to 1Gx32 of external memory. Separate sets of instructions and addressing modes are available for integer instructions and floating-point instructions. DAU instructions use a combination of register-direct and register-indirect addressing. CAU arithmetic instructions primarily use register-direct addressing, but immediate data, memory-direct addressing, and register-indirect addressing with optional post-increment are used by some CAU instructions. Because the CAU doubles as an address generation unit and an integer data path, the programmer can readily perform explicit address arithmetic in the CAU to implement other addressing modes that are not directly supported by the DSP32xx. Unlike the DSP32C, the DSP32xx does not support zero-overhead bit-reversed addressing. For a complete evaluation of this processor, including BDTI Benchmark ™ results, contact BDTI.
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