
Floating-Point DSP Processors
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Lucent Technologies DSP32C

The Lucent Technologies DSP32C is a 32-bit floating-point processor, first introduced in 1988. It is the successor to the DSP32. The DSP32C is capable of 20 MIPS with an 80 MHz input clock, and is only available with a 5.0-volt power supply. Peripherals include both serial and parallel I/O ports. Lucent Technologies has handed off responsibility for application development tools for the DSP32C to another company, Valley Technologies.

The DSP32xx family, (comprised of the DSP3207 and DSP3210) expands on the features of the DSP32C, but is on the verge of being discontinued. The DSP32xx family is covered in a separate summary page.

The DSP32C uses two separate data paths: a floating-point data path (called the data arithmetic unit or DAU) and an integer data path/address generation unit (called the control arithmetic unit or CAU). The CAU acts both as a 24-bit integer data path and as an address generation unit, and consists of twenty-two 24-bit registers and an integer arithmetic logic unit. The processor does not use IEEE standard 754 floating-point formats or arithmetic, but does provide single-cycle conversion between the native floating-point format and IEEE format, in both directions. The floating-point data path of the DSP32C incorporates a 32x32->45-bit floating-point multiplier, a 40-bit adder, and four 40-bit accumulators. Unlike other floating-point DSPs, the DSP32C floating-point data path is not capable of performing arithmetic on integer values. Instead, integer arithmetic is handled in the CAU.

The DSP32C uses a modified Von Neumann memory architecture with a single memory space and a single set of address and data buses. The memory space contains up to four physically separate memory banks: three 512x32 on-chip RAMs, and one off-chip memory bank. Instructions and data can reside in any of these banks. The processor achieves multiple memory accesses per instruction cycle by multiplexing accesses over the single bus set. Four accesses can be completed per instruction cycle, assuming that successive memory accesses use different memory banks. If a program attempts more accesses than are allowed, the processor automatically inserts conflict wait states. The DSP32C provides a single 22-bit address, 32-bit data external memory interface with four byte-select lines. The 22 bits of the address specify a 32-bit word, and the byte-select lines specify the needed bytes within the 32-bit word. Thus, the processor can address up to 4Mx32 of external memory. All internal and external memory is byte-addressable.

Separate sets of instructions and addressing modes are available for integer instructions and floating-point instructions. DAU instructions use a combination of register-direct addressing and register-indirect addressing. CAU arithmetic instructions primarily use register-direct addressing, but immediate data, memory-direct addressing, and register-indirect addressing with optional post-increment are used by other CAU instructions. Bit-reversed addressing is supported through the use of reverse-carry arithmetic in the CAU. Because the CAU doubles as an address generation unit and an integer data path, the programmer can readily perform explicit address arithmetic in the CAU to implement other addressing modes that are not directly supported by the DSP32C.

As of July 1997, the 80-MHZ version of the processor in a 164-pin BQFP sold for $75.00 in quantity 1,000. For a complete evaluation of this processor, including BDTI Benchmark ™ results, contact BDTI.

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