General-Purpose Processors
|
||
General-Purpose Processors |
|
|
| HOME << |
|
|
|
||
ARM ARM9EThe ARM9E, first announced in May 1999, is a 32-bit licensable RISC microprocessor core developed by ARM Limited. The ARM9E is projected to achieve 200 MHz (worst-case) at 1.8 volts in a 0.18-micron process; other fabrication processes may yield different speeds. The ARM9E bears a strong resemblance to its predecessor, the ARM9. The main difference between these processors is the addition of DSP-oriented enhancements to the ARM9E instruction set, including single-cycle 16-bit MAC operations, saturating arithmetic, and normalization. The ARM9E uses 32-bit instructions, and supports “Thumb” mode, in which a subset of 32-bit instructions is compressed into 16-bit instructions to improve code density. The ARM9E is a single-issue 32-bit RISC architecture that consists of a program control unit, an address generator, and a fixed-point integer data path. The data path contains a 32-bit ALU, a 32 × 32 multiply-accumulate unit, and a barrel shifter. The data path has sixteen 32-bit registers (R0-R15) that serve as source and destination operands and as address registers. R15, R14, and R13 also serve as the program counter, link register, and stack pointer, respectively; the remaining registers are available for general use. Several of the registers have shadow registers that are swapped with their corresponding registers when the processor enters an exception mode. The ARM9E multiply-accumulate unit supports signed or unsigned, 32 × 32 ® 32 (“single-precision”) or 32 × 32 ® 64 (“double-precision”) integer multiplications. Any general-purpose register can serve as an accumulator for single-precision multiply operations. In double-precision multiply operations, any combination of two general-purpose registers can be specified to form the 64-bit accumulator. The ARM9E provides no guard bits for 32 × 32 multiplications. Single-precision multiply operations include multiply, multiply-add, and multiply-accumulate. Double-precision multiply operations support only multiply and multiply-accumulate. The ARM9E multiply-accumulate unit also supports signed integer 32 × 16 and 16 × 16 multiplies, multiply-adds, and multiply-accumulates. Each 16-bit input can be taken from the high or low half of a 32-bit register. The 32-bit result can be stored in a 32-bit register; the ARM9E also supports a 16 × 16 ® 64 multiply-accumulate operation that provides 32 guard bits. The ARM9E ALU supports addition and subtraction (with or without carry) including saturating add and subtract instructions. The ARM9E supports “double-saturating” versions of these instructions that left-shift one source operand by one (which removes the extra sign bit generated by multiplying two fractional values), saturate the left-shifted value, and then add/subtract this result to/from the other source operand. The final result is saturated again before writing to the destination register. The ALU also supports and, or, and xor operations, bit clear/test, 32-bit comparisons, and a count leading zeros (CLZ) instruction that supports normalization by computing the number of zeroed high-order bits of a source operand. The ARM9E does not support rounding. The barrel shifter performs logical shift left, logical shift right, arithmetic shift right, and rotate right operations. The barrel shifter can shift one of the ALU input operands prior to an ALU operation. If the shift is specified by an immediate operand, this shift operation is executed in the same cycle as the ALU instruction. A shift cannot be performed in the same cycle as a multiply, saturating arithmetic, or normalization instruction. The ARM9E uses a Harvard memory architecture with separate buses for instructions and data. The ARM9E supports up to one data transfer and one instruction transfer per cycle. The ARM9E supports byte, 16-bit aligned half-word, and 32-bit aligned word data transfers, and supports both big-endian and little-endian byte ordering. The ARM9E also supports multiple-word load and store instructions that use a single instruction to transfer up to sixteen 32-bit data words to/from consecutive memory locations at a rate of one 32-bit word per cycle. With zero-wait-state memory and an operating speed of 200 MHz, the ARM9E can achieve a maximum sustainable memory bandwidth of 400 million 16-bit half-words/second. Addressing modes supported by the ARM9E include register-direct, register-indirect with pre- or post-increment/decrement, and register-indirect with indexing. Multiple-word loads and stores support register-indirect addressing with pre- or post-increment. Single-word load and store instructions support register-indirect addressing with pre- or post-increment/decrement. The ARM9E does not support bit-reversed addressing or modulo (circular) addressing. The ARM9E does not support hardware looping. The ARM9E core does not include memory or a cache. However, ARM offers the ARM9E only as part of a processor “macrocell” that generally includes an ARM core, a memory management unit, and an integrated cache. ARM9E-based macrocell caches are split between instructions and data. Cache associativities range from 4-way to 64-way set associative, and replacement algorithms are either random or round-robin. Caches support write-back and/or write-through operation, and most caches support locking of individual cache regions. ARM9E-based processor macrocells support instruction cache preloading via special prefetch operations. Power consumption for ARM9E-based chips will vary from chip to chip. LSI Logic states that its implementation of an ARM9E processor macrocell with 32 Kbytes of cache is projected to consume 380 mW at 200 MHz (in LSI’s 0.18-micron process at 1.8 volts). The ARM9E is a processor core intended for use as part of a complete chip, and as such it does not have a fixed per-unit price. ARM9E-based chip prices will vary; contact manufacturer for pricing information. License fees are not disclosed by ARM; contact ARM for license fee information. A complete analysis of the ARM9E, including BDTI Benchmark™ results, is contained in BDTI’s report, Inside the ARM ARM7, ARM9, and ARM9E.
|