General-Purpose Processors
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General-Purpose Processors |
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ARM ARM9The ARM9, first announced in 1997, is a 32-bit licensable RISC microprocessor core developed by ARM Limited. Numerous manufacturers offer packaged microcontrollers and application-specific standard products (ASSPs) based on ARM9 cores. The fastest ARM9-based processors in production operate at 200 MHz with a 1.8 V power supply. The ARM9 implements the same instruction set as the older ARM7, and these cores are binary cross-compatible. The two cores are not identical, however; for example, the ARM9 has a deeper pipeline than the ARM7 (five stages versus three) and uses a Harvard memory architecture rather than the Von Neumann architecture of the ARM7. ARM also offers a DSP-enhanced version of the ARM9, the ARM9E, for applications that require higher DSP performance than that provided by the ARM9. The ARM9 uses 32-bit instructions and supports “Thumb” mode, in which a subset of 32-bit instructions is compressed into 16-bit instructions to improve code density. The ARM9 is a single-issue 32-bit RISC architecture that consists of a program control unit, an address generator, and a fixed-point integer data path. The data path contains a 32-bit ALU, a 32 × 32 multiply-accumulate unit, and a barrel shifter. The data path has sixteen 32-bit registers (R0-R15) that serve as source and destination operands and as address registers. R15, R14, and R13 also serve as the program counter, link register, and stack pointer, respectively; the remaining registers are available for general use. Several of the registers have shadow registers that are swapped with their corresponding registers when the processor enters an exception mode. The ARM9 multiply-accumulate unit supports signed or unsigned, 32 × 32 ® 32 (“single-precision”) or 32 × 32 ® 64 (“double-precision”) integer multiplications. Any general-purpose register can serve as an accumulator for single-precision multiply operations. In double-precision multiply operations, any combination of two general-purpose registers can be specified to form the 64-bit accumulator. The ARM9 provides no guard bits for 32 × 32 multiplications. Single-precision multiply operations include multiply, multiply-add, and multiply-accumulate. Double-precision multiply operations support only multiply and multiply-accumulate. All ARM9 multiplier operations have data-dependent timings. Depending on the contents of the input data and the type of multiplication, these processors require between two and seven cycles (for both throughput and latency) to complete the operation. The ARM9 ALU supports addition and subtraction (with or without carry), and, or, and xor operations, bit clear/test, and 32-bit comparisons. The ARM9 does not support rounding or saturation, nor does it offer a count-leading-zeros operation. The barrel shifter performs logical shift left, logical shift right, arithmetic shift right, and rotate right operations. The barrel shifter can shift one of the ALU input operands prior to an ALU operation. If the shift is specified by an immediate operand, this shift operation is executed in the same cycle as the ALU instruction. A shift cannot be performed in the same cycle as a multiply. The ARM9 uses a Harvard memory architecture, with separate buses for instructions and data. The ARM9 supports up to one data transfer and one instruction transfer per cycle. The ARM9 supports byte, 16-bit aligned half-word, and 32-bit aligned word data transfers, and supports both big-endian and little-endian byte ordering. The ARM9 also supports multiple-word load and store instructions that use a single instruction to transfer up to sixteen 32-bit data words to/from consecutive memory locations at a rate of one 32-bit word per cycle. With zero-wait-state memory and an operating speed of 200 MHz, the ARM9 can achieve a maximum sustainable memory bandwidth of 400 million 16-bit half-words/second. Addressing modes supported by the ARM9 include register-direct, register-indirect with pre- or post-increment/decrement, and register-indirect with indexing. Multiple-word loads and stores support register-indirect addressing with pre- or post-increment. Single-word load and store instructions support register-indirect addressing with pre- or post-increment/decrement. The ARM9 does not support bit-reversed addressing or modulo (circular) addressing. The ARM9 does not support hardware looping. The ARM9 core does not include memory or a cache. However, ARM offers the ARM9 only as part of a processor “macrocell” that generally includes an ARM core, a memory management unit, and an integrated cache. ARM9-based macrocell caches are split between instructions and data. Cache associativities range from 4-way to 64-way set associative, and replacement algorithms are either random or round-robin. Caches support write-back and/or write-through operation, and most caches support locking of individual cache regions. ARM9-based processor macrocells support instruction cache preloading via special prefetch operations. ARM9-based chips are manufactured by several vendors and power consumption varies from chip to chip. The ARM9 is a processor core intended for use as part of a complete chip, and as such it does not have a fixed per-unit price. ARM9-based chip prices will vary; contact manufacturer for pricing information. License fees are not disclosed by ARM; contact ARM for license fee information. A complete analysis of the ARM9, including BDTI Benchmark™ results, is contained in BDTI’s report, Inside the ARM ARM7, ARM9, and ARM9E.
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