General-Purpose Processors
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General-Purpose Processors |
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ARM ARM7TDMIThe ARM7TDMI is a 32-bit RISC microprocessor core developed by ARM. ARM licenses the ARM7TDMI to several manufacturing partners, including Sharp, Texas Instruments, GEC Plessey, VLSI Technology, Cirrus Logic, and Samsung. These partners offer microprocessors and FASICs with a variety of peripherals designed around the ARM7TDMI core. ARM is targeting the ARM7TDMI at embedded applications requiring a very low-cost, low-power processor with high code density. The fastest ARM7TDMI-based processor in production as of this writing runs at 40 MIPS with a 3.3 V power supply. The ARM7TDMI core is an extension of the ARM7 core, which was introduced in 1993. The ARM7 is object code-compatible with its predecessor, the ARM6 core, but has increased performance and added features. The ARM7 is one of several cores in ARM's product line. Users requiring higher performance than available on the ARM7 may upgrade to the object code-compatible ARM8 or StrongARM cores. Both the ARM8 and StrongARM use architectural enhancements to run with instruction execution rates far exceeding that of the ARM7TDMI. The ARM7TDMI does not have any DSP-specific features. For applications requiring higher DSP performance, ARM licenses the ARM9E The ARM7TDMI is a 32-bit RISC architecture that consists of a program control unit, an address generator, an integer data path, and a general-purpose register bank. The ARM7TDMI data path contains a 32-bit integer ALU, a multiply-add unit, a barrel shifter, and a bank of sixteen 32-bit general-purpose registers. The ARM7TDMI does not support floating-point arithmetic in hardware. General-purpose registers are used for addressing and serve as operand sources and destinations for instructions using the ALU, multiplier, or barrel shifter. One of the general-purpose registers, R15, is used to hold the program counter. R13 and R14 serve as a stack pointer and link register, respectively, leaving 13 general-purpose registers available for use as operand sources or destinations when a stack pointer and link register are needed. Several of the general-purpose registers have shadow registers which are swapped with normal general-purpose registers when the processor enters interrupt service routines. The ARM7TDMI's 32-bit ALU performs simple integer arithmetic operations such as add and subtract. Two 32-bit data buses connect the general-purpose register file to the ALU and supply the input operands. A third 32-bit data bus returns ALU output operands to the general-purpose register file or to the address generation unit. One of the input operand data buses that connects the general-purpose register file to the ALU passes through the barrel shifter. The barrel shifter allows one of the ALU input operands to be shifted by up to 31 bits prior to ALU operations. The ARM7TDMI features a multi-cycle 32x32->64-bit multiplier. The ARM7TDMI multiplier employs an early termination algorithm that multiplies multiplicands in 8-bit stages. If at any point all of the remaining bits of either multiplicand are zero in the case of positive numbers, or one in the case of negative numbers (thus, assuring the remaining product will be zero), the multiply terminates. Each 8-bit multiply stage requires one instruction cycle to execute. Thus, an ARM7TDMI multiply instruction can take as little as two cycles (one to load the instruction and one for the first-stage multiply) or as many as five cycles (one to load the instruction and four for all four multiply stages). Some multiply and multiply-add instructions, called long multiply instructions by ARM, store or add the 64-bit product to two 32-bit general-purpose registers. Normal multiply and multiply-add instructions store or add only the lower 32 bits of the product. When using normal multiply and multiply-add instructions, programmers must be careful to scale input operands so that all significant output bits are contained in the lower 32 bits of the result since no guard bits are available. The ARM7TDMI does not support saturation arithmetic. The ARM7TDMI core does not contain any memory. The ARM7TDMI has a single 32-bit memory space accessed by a 32-bit data bus and a 32-bit address bus. Since the ARM7TDMI has just one bus set, only one 32-bit memory access can be performed per clock cycle. Thus, single-word store instructions require two instruction cycles to execute—one cycle to fetch the instruction from memory, and one cycle to complete the data transfer. Single-word load instructions require three instruction cycles to execute—one cycle to fetch the instruction from memory, one cycle to complete the data transfer, and one cycle to save the data in a general-purpose register. ARM7TDMI data bandwidth can be increased by using multiple-word load and store instructions. With multiple-word loads and stores, each additional word moved after the first word requires just one additional instruction cycle. Addressing modes supported by the ARM7TDMI include register-direct, register-indirect with pre- or post-increment/decrement, and indexed register-direct. Immediate data is also supported. At the time of this writing, none of ARM's manufacturing partners offered the ARM7TDMI core in the form of a simple, general-purpose processor. However, the ARM7TDMI core is contained in many FASICs. Because FASICs usually combine the core with other application-specific silicon blocks, projecting the cost of a more generic ARM7TDMI-based processor is difficult. A complete analysis of the ARM7TDMI, including estimated BDTI Benchmark™ results, is contained in BDTI's report, DSP on General-Purpose Processors.
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