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Analog Devices ADSP-21xxx (SHARC)

The ADSP-21xxx “SHARC” is the successor to the original ADSP-2106x “SHARC” family. Like the ADSP-2106x, the ADSP-21xxx is a 32-bit floating-point DSP processor with 48-bit instruction words. The ADSP-21xxx targets a variety of applications including consumer, automotive, professional audio, industrial, and medical imaging applications. The ADSP-21xxx is very similar to the ADSP-2106x, but compared to the ADSP-2106x, the ADSP-21xxx has a duplicated data path and widened on-chip buses to support SIMD (single-instruction, multiple-data) processing. The ADSP-21xxx can execute ADSP-2106x assembly source code without modification; however, to take advantage of the SIMD features, software written for the ADSP-2106x must be modified.

The newest ADSP-21xxx family members, the ADSP-2136x, use a slightly longer pipeline and a slightly different memory system than previous ADSP-21xxx family members. Due to these differences, software optimized for the older ADSP-21xxx family members must be modified to obtain optimal performance on the ADSP-2136x.

The first ADSP-21xxx family member, the ADSP-21160, was announced in June 1998. The ADSP-21xxx family currently includes twelve members. Ten of these family members are either sampling or shipping at speeds up to 333 MHz. The two newest parts, the ADSP-21367 and ADSP-21368, are expected to begin sampling in the first quarter of 2005. These new parts are expected to operate at 400 MHz.

Architecture

The ADSP-21xxx uses a 32-bit address space and 48-bit instruction word and contains two identical data paths, each of which contains a multiply-accumulate unit, a shift unit, and an ALU. Except for floating-point multiply-accumulate operations, which use both the multiply-accumulate unit and the ALU, each data path is limited to using one execution unit per cycle. Each data path has a register file containing sixteen 40-bit registers; each data path takes operands from, and returns results to, its register file. The ADSP-21xxx supports four data types: 40- and 32-bit IEEE floating-point, 16-bit floating-point, and 32-bit fixed-point.

The ADSP-21xxx operates either in SISD (single-instruction, single-data) mode or in SIMD mode. When in SISD mode, the processor executes instructions in the “X” data path. The SIMD mode enables data path “Y,” which then executes the same operations as executed by data path “X,” but on the register file associated with data path “Y.”

The shift units perform single-bit manipulation, bit-field manipulation, rotation, and logical or arithmetic shifting operations. The multiply-accumulate units perform floating-point multiplication and fixed-point integer or fractional multiplication. Integer and fractional operands may be signed/signed, unsigned/unsigned or signed/unsigned, providing support for multi-precision arithmetic. When operating on floating-point data, the multiply-accumulate units perform 32 × 32 → 40-bit or 40 × 40 → 40-bit floating-point multiplication. When operating on fixed-point data, the multiply-accumulate units perform 32 × 32 → 64-bit multiplications, and each provides an 80-bit accumulator sub-unit (which yields 16 guard bits). The accumulators are used only for fixed-point operations; the ALU is used to perform accumulation on floating-point results.

ADSP-21xxx processors contain up to 512 Kbytes of unified instruction and data memory; this memory is divided evenly into two blocks. The ADSP-21xxx also includes a 32-instruction on-chip instruction cache. The ADSP-21xxx accesses on-chip memory through two sets of buses; each bus set consists of a 64-bit data bus and a 32-bit address bus. When executing instructions from on-chip memory, the ADSP-21xxx uses one of these bus sets to fetch instructions, and it uses the other bus set to transfer data. When executing instructions from cache, the processor can use both bus sets to transfer data; in this case, the ADSP-21xxx can load or store two pairs of 32-bit words per instruction cycle, resulting in a bandwidth of 1600 million 32-bit words/second for a 400 MHz ADSP-21xxx.

The ADSP-21xxx supports a range of 64-bit double- and 32-bit single-word data moves between the register files in each data path and memory. For example, one mode of moving data from memory to the two register files allows the programmer to specify that identical data is to be copied into both register files (so that both data paths are operating on the same data); another allows 64-bit data to be split between the two register files.

ADSP-21xxx addressing modes include indexed, register-indirect, memory-direct, and register-direct. In addition, one address register in each of the data address generators can perform bit-reversed addressing. The ADSP-21xxx also supports immediate data.

The ADSP-21xxx provides zero-overhead hardware looping through its DO instruction. A sequence of instructions of any length can be contained in a hardware loop.

Peripherals

ADSP-21xxx processors feature a DMA controller and serial ports. Some ADSP-21xxx processors include link ports, a host processor interface, a serial peripheral interface (SPI), timers, an “Input Data Port,” a parallel port, a “Digital Applications Interface,” and general-purpose I/O pins.

Power Consumption

According to Analog Devices, the ADSP-21262 consumes about 504 mW at 200 MHz and 1.2 V. This measurement is based on an FFT-like workload and includes the core, on-chip memory, and clocked (but inactive) peripherals.

Cost

As of the last quarter of 2004, quantity 10,000 pricing for the ADSP-21xxx ranges from about $10 to about $106.

For Additional Information

The ADSP-2116x/2126x achieves a BDTImark2000™ score of 1090 at 200 MHz. The ADSP-2136x achieves a BDTImark2000™ score of 2050 at 400 MHz. For more information and scores, click here. A complete analysis of this processor, including BDTI Benchmark™ results, is contained in BDTI’s report, Buyer’s Guide to DSP Processors, 2004 Edition.

Last updated January 2005.

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