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Analog Devices ADSP-TS20x

The ADSP-TS20x is a family of DSP processors from Analog Devices based on the VLIW “TigerSHARC” core first introduced in October of 1998. The ADSP-TS20x operates on a variety of data widths and supports fixed- and floating-point formats. The ADSP-TS20x family is targeted at high-performance applications, such as cellular and broadband wireless base stations, medical imaging, and military applications.

The ADSP-TS20x family currently includes the ADSP-TS201S, ADSP-TS202S, and ADSP-TS203S. The ADSP-TS201S contains an execution unit, the “Communications Logic Unit” (CLU), that is not present in the other two family members. The CLU supports instructions designed to accelerate common communications algorithms, and is used in some of the BDTI Benchmarks. The ADSP-TS201S is currently shipping at 600 MHz at 1.2 volts in a 0.13-micron process.

The ADSP-TS20x can execute up to four 32-bit instructions in a single clock cycle. These instructions are scheduled for execution by the compiler or assembly language programmer. Its VLIW architecture (called “static superscalar” by Analog Devices) and extensive SIMD capabilities allow the ADSP-TS20x to achieve a high degree of parallelism. Instructions operate on 8-, 16-, 32-, or 64-bit integer data or 32-bit or 40-bit floating-point data.

Architecture

As discussed above, the ADSP-TS20x is a VLIW architecture and can execute up to four 32-bit instructions per instruction cycle. ADSP-TS20x processors are based on two identical fixed/floating-point data paths, two identical address generation units, four 128-bit internal buses, six internal memory banks, and extensive I/O capabilities including support for multiprocessing.

The ADSP-TS20x provides two identical fixed/floating-point data paths (called X and Y). On the ADSP-TS201S, each data path has four distinct arithmetic units: a multiplier-accumulator, a shifter, an ALU, and a CLU. The ADSP-TS202S and ADSP-TS203S do not include the CLU and thus have three arithmetic units in each data path.

Each data path may execute one or two instructions per instruction packet. If one data path executes two instructions in an instruction packet, these instructions may employ any two of the ALU, multiplier, shifter, or CLU (if present). Furthermore, an instruction can be simultaneously executed in both X and Y data paths. Instructions can also be executed in the address generation units.

The ADSP-TS20x supports two types of SIMD operations. Using SIMD operations, up to eight 8-bit, four 16-bit, or two 32-bit fixed-point operands may be processed by each data path, producing individual results as wide as 32 bits. In addition, two 64-bit SIMD inputs can produce a 64-bit result. In some cases one data path may produce SIMD result groups of up to 128 bits via one instruction; for example, multiplying four 16-bit operands by four 16-bit operands to produce four 32-bit products.

In addition to the usual fixed- and floating-point arithmetic operations, the data path ALUs support average ([A+B]/2, [A-B]/2), increment, decrement, minimum, maximum, compare (signed and unsigned), clipping (saturation where the limit is specified as an operand of the instruction), simultaneous add/subtract ([A+B], [A-B]), and permute operations.

The data path shifter units perform single-bit manipulation, bit-field manipulation, and shifting operations of up to 64 bits left or right.

The multiplier-accumulator units support floating-point and fixed-point integer or fractional multiplication and accumulation. There is no floating-point multiply-accumulate instruction, however. The multiplier-accumulator units support 20-, 40-, and 80-bit saturation for fixed-point arithmetic. There is a special instruction to multiply-accumulate two pairs of 16-bit complex numbers (each with 16 bits real, 16 bits imaginary) to produce dual complex results (again each with 16 bits real, 16 bits imaginary). The complex conjugate of one of the operands may optionally be used as an input.

The 128-bit CLUs (present only in the ADSP-TS201S) operate on 8-, 16-, or 32-bit fixed-point data (they do not support floating-point operands). The CLUs support specialized communications-oriented operations to speed execution of, for example, Viterbi and turbo code decoding. These include maximum value functions used for Turbo and Viterbi decoding, an add-compare-select function, a despread function, and a “crosscorrelations” function that is equivalent to executing 16 despread functions in parallel. Most of these operations are available in SIMD variants; for example, the Viterbi maximum operation can process two 32-bit operands or four 16-bit operands.

There are two address generation units (J and K). Each address generation unit contains a memory access unit along with a fixed-point data path. Each AGU data path contains an ALU, a shifter, and a memory-mapped register file of thirty-two 32-bit registers. The address generation units can also execute certain arithmetic instructions.

The ADSP-TS20x memory system consists of on-chip 32-bit embedded DRAM partitioned into six segments, up to approximately four Gwords of general-purpose off-chip 32-bit memory, and off-chip multiprocessor memory consisting of the 32-bit internal memory of up to seven other ADSP-TS20x chips. The size of the six DRAM segments (and thus the total on-chip memory) varies depending on the family member. On the ADSP-TS201S the segments are 4 Mbits each, for a total of 24 Mbits (3 Mbytes); the ADSP-TS202S has a total of 1.5 Mbytes; the ADSP-TS203S has a total of 512 Kbytes.

Peripherals

The ADSP-TS20x on-chip peripherals include two timers (with a 64-bit count for each), four “link ports” (each eight bits wide instead of four bits as on the ADSP-2106x), a 14-channel DMA controller, and four bit-I/O pins. The external memory interface also functions as a host port.

Power Consumption

According to Analog Devices, the ADSP-TS201S consumes 2.18 W when the core operates at 500 MHz and 1.0 volts, and its on-chip DRAM operates at 250 MHz and 1.5 volts. This figure is based on a typical signal processing workload. It includes power for the core and on-chip memory, but excludes peripherals and I/O activity.

Cost

As of the last quarter of 2004, quantity 10,000 pricing for the ADSP-TS20x ranged from $47 for the TS203S to $197 for the 600 MHz TS201S.

For Additional Information

The TS201S achieves a BDTImark2000™ score of 6400 at 600 MHz. The TS202S and TS203S achieve a BDTImark2000™ score of 5130 at 500 MHz. For more information and scores, click here. A complete analysis of this processor, including BDTI Benchmark™ results, is contained in BDTI’s report, Buyer’s Guide to DSP Processors, 2004 Edition.

Last updated January 2005.

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