
Fixed-Point DSP Processors
HOME << FREE INFO << PROCESSOR OVERVIEWS <<

Analog Devices ADSP-21xx

The ADSP-21xx is the first DSP processor family from Analog Devices. The family consists of a large number of processors based on a common 16-bit fixed-point architecture with a 24-bit instruction word. The ADSP-21xx is also available as a licensable core for use in ASICs. As of October 1998, the fastest members of the family operate at 75 MIPS at 2.5 volts, 52 MIPS at 3.3 volts, and 40 MIPS at 5.0 volts. Analog Devices has recently announced the ADSP-219x series, which offers projected speeds of up to 300 MIPS, as well as architectural enhancements. ADSP-21xx processors are targeted at modem, audio, PC multimedia, and digital cellular applications.

The ADSP-21xx data path consists of three separate arithmetic execution units: an arithmetic/logic unit (ALU), a multiplier/accumulator (MAC), and a barrel shifter. Each unit is capable of single-cycle execution, but only one of these units can be active during a single instruction cycle. The ALU operates on 16-bit data. In addition to the usual ALU operations, the ALU provides increment/decrement, absolute value, and add-with-carry functions. ALU results are saturated upon overflow if the appropriate configuration bit is set by the programmer. The MAC unit includes a 16x16->32-bit multiplier, four input registers (two for each memory space, PM and DM), a feedback register, a 40-bit adder, and a single 40-bit result register/accumulator providing eight guard bits. Besides signed operands, the multiplier can operate on unsigned/unsigned or on signed/unsigned operands, thus supporting multi-precision arithmetic. The barrel shifter shifts 16-bit inputs from an input register or from the ALU/MAC/barrel shifter result registers into a 32-bit result register. Logical and arithmetic shifts are supported left or right up to 32 bits. The barrel shifter also supports block floating-point arithmetic with block exponent detect (which determines a maximum exponent of a block of data), single-word exponent detect, normalize, and exponent adjust instructions.

ADSP-21xx processors use a modified Harvard architecture with separate memory spaces and on-chip bus sets for program and data. All processors in the ADSP-21xx family, except the ADSP-2100A, include on-chip program RAM or ROM and on-chip data RAM. The ADSP-2100A has no on-chip memory; instead it has a 16-word instruction cache and two external bus sets.

On-chip program memory can be used for both instructions and data, and it can be accessed via a 14-bit address bus and a 24-bit data bus. On-chip program memory is dual-ported to allow the processor to fetch both a data operand and the next instruction in a single instruction cycle. The on-chip data memory can be accessed via a 14-bit address bus and a 16-bit data bus. One access to the on-chip data memory can be performed in a single instruction cycle. Three memory accesses (one instruction and two data operands) can be performed in one instruction cycle (except on the ADSP-2100A which has no on-chip memory). On a 75 MIPS ADSP-2189M this results in a maximum sustainable on-chip data memory bandwidth of 150 16-bit Mwords/second.

Both of the on-chip memory spaces can be extended off-chip. All ADSP-21xx processors except the ADSP-2100A have one external memory interface, providing a 14-bit address bus and a 24-bit data bus. This external interface is multiplexed between program and data memory accesses.

The ADSP-21xx supports register-direct, memory-direct and register-indirect addressing modes. Immediate data is also supported.

The ADSP-21xx provides zero-overhead program looping through its DO instruction. Any length sequence of instructions can be contained in a hardware loop, and up to 16,384 repetitions are supported.

The ADSP-2100A has no on-chip peripherals. All other family variants incorporate one or more serial ports, a timer, a bit I/O port, and in some cases a host port, a 16-bit codec, and/or two DMA controllers.

As of October 1998, quantity 10,000 prices for ADSP-21xx family members range from $5.00 to $79.00. A complete analysis of this processor, including BDTI Benchmark™ results, is contained in BDTI's report, Buyer's Guide to DSP Processors, 2001 Edition.

Top of page