Analog Devices ADSP-21cspxx

The Analog Devices ADSP-21cspxx is a 16-bit fixed-point DSP family with 24-bit instructions. The only ADSP-21cspxx family member currently available, the ADSP-21csp01, was introduced in 1995. As of March 1997, the ADSP-21csp01 operates at up to 50 MIPS at 5.0 volts. The ADSP-21cspxx family is targeted at computer and telecommunications applications where simultaneous manipulation of several signals is required, such as voice-over-data modems, cellular base stations, and computer telephony systems.

The ADSP-21cspxx architecture is similar to that of the ADSP-21xx family, but adds a number of significant architectural enhancements. The ADSP-21cspxx is nearly assembly source-code compatible with the ADSP-21xx.

The ADSP-21cspxx implements a load-store architecture: source operands for arithmetic operations must be loaded into registers before computation. Similarly, the results of arithmetic operations must be stored to a register. Like the ADSP-21xx, the ADSP-21cspxx uses a 16-bit fixed-point data path consisting of three separate arithmetic execution units: an ALU, a multiply-accumulate (MAC) unit, and a barrel shifter. All of these units are capable of single-cycle execution, but only one unit can be active at a time.

The ALU operates on 16-bit data. It includes four 16-bit input registers, a 16-bit feedback register (to return results to the input of the ALU for further processing), and a 16-bit result register. In addition to the usual ALU operations, the ALU provides increment/decrement, absolute value, bit set/clear/toggle, add-with-carry, and subtract-with-borrow functions. ALU results are saturated upon overflow if the appropriate configuration bit is set by the programmer. The MAC unit includes a 16x16->32-bit multiplier integrated with a 40-bit adder. The MAC unit has four 16-bit input registers and two 40-bit accumulators with eight guard bits. The second accumulator is also used as the shifter result register. The multiplier supports signed, signed/unsigned, and unsigned multiplications. 32-bit multiplication results are rounded to 16 bits if a rounding specifier is used in the instruction. The rounding scheme can be either round-to-nearest (biased) or convergent (unbiased) depending on a bit stored in a control register. The multiplier provides an optional one-bit left shift of results to allow either fractional or integer multiplies. The barrel shifter shifts 16-bit inputs from a dedicated input register or from a 16-bit portion of an ALU/MAC/barrel shifter result register. Logical and arithmetic shifts are supported left or right up to 40 bits. Shift results can be merged (logically or'd) with previous shift results. The barrel shifter also supports block floating-point arithmetic with block exponent detect, single-word exponent detect, normalize, and exponent adjust instructions.

The ADSP-21cspxx implements a modified Harvard architecture with two separate on-chip bus sets and a single, unified address space. The ADSP-21csp01 on-chip memory consists of four Kwords of 24-bit program/data RAM and four Kwords of 16-bit data RAM. The on-chip memories are accessed via two pairs of address and data buses. The data bus for program/data memory is 24 bits wide, which allows it to carry either 24-bit instructions or 16-bit data. The data bus for data memory is 16 bits wide. The independent program/data and data memory buses let the ADSP-21cspxx processor core simultaneously access two data words from two different 2 Kword on-chip memory blocks. If the core tries to simultaneously access two data words from the same memory block, an extra cycle is needed. In order for instructions requiring two data accesses to achieve single-cycle execution, the current instruction must be fetched from the processor's 64-entry, two-way set-associative cache. Assuming that instructions are fetched from the instruction cache and data operands reside in separate memory blocks, the maximum sustainable on-chip data memory bandwidth is 100 Mwords/second with a 50 MIPS ADSP-21csp01.

The external memory interface of the ADSP-21cspxx provides a 24-bit address bus and a 24-bit data bus. These buses are multiplexed between 24-bit instruction and 16-bit data accesses. The ADSP-21cspxx can have up to 16 Mwords of external unified program and data memory. The ADSP-21cspxx also has two additional memory spaces: I/O memory and boot memory. Programmable and externally requested wait states are supported. Assuming zero wait states, the ADSP-21cspxx is capable of accessing one program or data word in external memory in a single instruction cycle. With a 50 MIPS ADSP-21csp01, this results in a maximum sustainable external memory bandwidth of 50 Mwords/second.

The ADSP-21cspxx includes two data address generators. The ADSP-21cspxx supports immediate data and register-direct, memory-direct, register-indirect, indexed, and PC-relative addressing. Circular addressing is also supported via the modulo start and modulo length registers. Bit-reversed addressing is supported by one of the address generators.

The ADSP-21cspxx supports hardware looping through its DO instruction.

ADSP-21csp01 peripherals include two serial ports, a bit I/O port, a timer, and a DMA port.

As of March 1997, quantity 1,000 pricing for the 50 MIPS ADSP-21csp01 in a 160-pin PQFP package is $40.00. For a complete evaluation of this processor, including BDTI Benchmark™ results, contact BDTI.