Analog Devices ADSP-219x and ADSP-2199xThe Analog Devices ADSP-219x and ADSP-2199x are 16-bit fixed-point DSPs with 24-bit instructions. The ADSP-219x core used in both families is based on the ADSP-218x architecture, but has a number of architectural enhancements. Most important among these are the addition of new addressing modes, an expanded address space, the addition of an instruction cache, and a deeper pipeline (six stages, compared to three on the ADSP-218x) to enable faster clock speeds. The ADSP-219x is mostly, but not completely, assembly source code upward compatible with the ADSP-218x. The ADSP-219x and ADSP-2199x target low-cost applications; the ADSP-2199x is particularly focused on motor control applications. There are three members in the ADSP-219x family and three members in the ADSP-2199x family. All six parts operate at 2.5 V; the fastest parts operate at 160 MHz. ArchitectureThe ADSP-219x architecture includes a 16-bit data path, two data address generators, a program control unit, an instruction cache, and a unified program/data memory space. The data path consists of three separate arithmetic execution units: an ALU, a MAC unit, and a barrel shifter. Each of these units is capable of single-cycle execution, but only one unit can be active during a single instruction cycle. The ADSP-219x includes sixteen 16-bit data registers and, in contrast to the ADSP-218x family, all of these registers can be used by all three execution units (with a few limitations for conditional ALU/MAC instructions). The ALU operates on 16-bit data. The MAC unit performs 16 × 16 → 32-bit multiplies, storing results in one of two 40-bit accumulators, each of which provides eight guard bits. The barrel shifter shifts 16-bit inputs from any 16-bit input register and stores results in a 40-bit result register.The ADSP-219x memory system provides a unified, word-addressable space that contains both instructions and data. The internal and external memory is physically organized into 256 pages of 64 Kwords each. Every memory page contains a block of 24-bit memory that can contain either instructions or data, and a block of 16-bit memory that contains only data. The distribution of 16-bit and 24-bit memory vary among different family members. The 24-bit memory block is accessed by a 24-bit program address bus and a 24-bit program data bus. The 16-bit memory block is accessed by a 24-bit data address bus and a 16-bit data bus. The ADSP-219x provides a 64-word instruction cache. This cache only stores instructions that access data memory with the PM buses; the cache is similar to the cache used in Analog Devices’ SHARC (ADSP-2106x) family. The maximum on-chip data memory bandwidth of a 160 MHz ADSP-219x core is 320 million 16-bit words/second. The ADSP-219x has two address generators, each of which can generate both data and program memory addresses. The ADSP-219x supports register-direct, memory-direct, register-indirect, indexed, modulo, bit-reversed, post-increment with immediate data, and immediate data write to memory addressing modes. The ADSP-219x contains four hardware loop counters that support single- and multi-instruction hardware looping. Four-level nesting of hardware loops is allowed. Hardware loops are interruptible. PeripheralsADSP-219x and ADSP-2199x peripherals include a DMA controller, a host port, serial ports, a serial peripheral interface, a UART, and timers. The ADSP-2199x also provides 14-bit analog-to-digital converters.Power ConsumptionThe ADSP-219x consumes 525 mW at 160 MHz and 2.5 V under a 50% MAC, 50% register load/store workload. This measurement includes the core and on-chip memory.CostAs of the last quarter of 2004, quantity 10,000 pricing for the ADSP-219x and ADSP-2199x ranged from $9.99 for the ADSP-2196M to $23.95 for the ADSP-21992.For Additional InformationThe ADSP-219x and ADSP-2199x achieve a BDTImark2000™ score of 410 at 160 MHz. For more information and scores, click here. A complete analysis of this processor, including BDTI Benchmark™ results, is contained in BDTI’s report, Buyer’s Guide to DSP Processors, 2001 Edition.Last updated January 2005. |
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