DSP Cores
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Analog Devices ADSP-2106xThe ADSP-2106x ``SHARC'' is a family of 32-bit floating-point DSP processors with 48-bit instruction words from Analog Devices. The ADSP-2106x is targeted at military, audio, voice recognition, imaging, and telephony applications, especially those requiring multiprocessor systems. The fastest members of the ADSP-2106x family available as of October 1998 run at 60 MIPS at 3.3 volts and 50 MIPS at 5.0 volts. The ADSP-2106x has been available since September 1994, and is based on Analog Devices' earlier ADSP-21020 architecture. The ADSP-2106x is object-code compatible with the ADSP-21020. In 1998, Analog Devices announced a SIMD successor to the ADSP-2106x, the ADSP-2116x family. ADSP-2106x processors are based on a common 40-bit floating-point data path, program control unit, bus structure, and I/O interfaces, but feature different amounts of on-chip memory and different peripheral configurations. The ADSP-2106x uses a 32-bit address space and 48-bit instruction word. As in Analog Devices' ADSP-21xx fixed-point DSP processors, the ADSP-2106x provides three distinct arithmetic units: a multiplier-accumulator, a shifter, and an ALU, all of which perform arithmetic and logical operations in a single instruction cycle. Unlike the ADSP-21xx, however, on the ADSP-2106x the multiplier-accumulator, the shifter, and the ALU all access a common register file containing sixteen 40-bit registers. The shifter unit performs single-bit manipulation, bit-field manipulation, rotation, and logical or arithmetic shifting operations. The multiplier unit performs floating-point multiplication and fixed-point integer or fractional multiplication. Integer and fractional operands may be signed/signed, unsigned/unsigned or signed/unsigned. These features provide support for multi-precision arithmetic. When operating on floating-point data, the multiplier unit performs 32x32->40-bit or 40x40->40-bit floating-point multiplication. When operating on fixed-point data, the multiplier unit performs 32x32->64-bit multiplication and provides an 80-bit accumulator sub-unit (which yields 16 guard bits). The accumulator is used only for fixed-point operations; the ALU is used to perform accumulation on floating-point results. The ADSP-2106x supports four data types: 40-bit and 32-bit IEEE floating-point, 16-bit floating-point, and 32-bit fixed-point. The ADSP-2106x memory system consists of either 512 Kbytes, 256 Kbytes, or 128 Kbytes (depending on the processor model) of on-chip memory evenly divided into two blocks, up to three Mwords of off-chip multiprocessor memory (memory that physically resides in other ADSP-2106x processors), and up to four Gwords of general-purpose off-chip memory. Memory is arranged in a unified, word-addressable address space that contains both instructions and data. Separate address generators, address buses, and data buses allow both on-chip memory blocks to be accessed by the core processor in a single instruction cycle. In addition, the ADSP-2106x includes a 32-word on-chip instruction cache which can be used to improve the effective memory bandwidth. The maximum sustainable data memory bandwidth for a 60 MIPS ADSP-2106x is 120 32-bit Mwords/second for reads or writes, assuming instructions are executed from cache. External memory consists of off-chip RAM or ROM that is accessed via the ADSP-2106x external memory interface. One set of address and data buses is brought off-chip. The address bus is 32 bits wide, which allows the processor to access 4 Gwords of multiprocessor or external memory. The data bus is 48 bits wide to accommodate the 48-bit instruction width. The maximum sustainable off-chip memory bandwidth for a 50 MIPS ADSP-2106x is 50 Mwords/second of either 48-bit instructions or 32-bit data. The ADSP-21065L is an exception: its external data bus is 32 bits wide. A 60 MIPS ADSP-21065L has a maximum sustainable off-chip memory bandwidth of 60 Mwords/second, but only for 32-bit data. ADSP-2106x addressing modes include indexed, register-indirect, memory-direct, and register-direct. In addition, one address register in each of the data address generators can perform bit-reversed addressing. The ADSP-2106x also supports immediate data. The ADSP-2106x provides zero-overhead hardware looping through its DO instruction. A sequence of instructions of any length can be contained in a hardware loop. The ADSP-2106x on-chip peripherals include a timer, two serial ports, six "link ports" (not available on the ADSP-21061), a ten-channel DMA controller (six-channel on the ADSP-21061), four bit-I/O pins, and a host port. As of October 1998, quantity 10,000 prices for ADSP-2106x family members range from $20.00 to $381.00. A complete analysis of this processor, including BDTI Benchmark™ results, is contained in BDTI's report, Buyer's Guide to DSP Processors, 2001 Edition.
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