Analog Devices ADSP-21020

While still manufactured by Analog Devices, the ADSP-21020 has been largely superseded by the faster, more feature-rich, and less expensive ADSP-2106x, the first versions of which became available in 1994. The ADSP-2106x and ADSP-21020 share virtually identical core architectures and the ADSP-2106x executes ADSP-21020 object code. However, the ADSP-2106x adds substantial amounts of on-chip RAM, peripherals, and I/O interfaces not found on the ADSP-21020.

The ADSP-210x0 family formerly included the 12.5 MIPS ADSP-21010, which was similar in architecture to the ADSP-21020. The ADSP-21010 has been discontinued by Analog Devices.

The ADSP-21020 is notable for its powerful and orthogonal instruction set, unusual 48-bit instruction word width, shadowing of all arithmetic and address registers, and lack of on-chip memory.

As in Analog Devices' ADSP-21xx fixed-point DSPs, the ADSP-21020 provides three distinct arithmetic units: a multiplier-accumulator, a shifter, and an ALU. Unlike the ADSP-21xx, on the ADSP-21020 these units all access a common register file containing 16 40-bit registers. Inputs to all arithmetic operations come from the register file, and results of all arithmetic operations are delivered to the register file.

The ADSP-21020 supports three data types: 40-bit IEEE floating-point, 32-bit IEEE floating-point, and 32-bit fixed-point. The ADSP-21020 provides nearly complete hardware support for the IEEE single-precision floating-point format and arithmetic; the processor additionally supports the IEEE single-extended precision floating-point format (a 40-bit format that extends the single-precision mantissa by eight bits for added precision).

The ADSP-21020 provides a 32-bit address space and uses an unusually large 48-bit instruction word. Like Analog Devices' fixed-point ADSP-21xx processors, the ADSP-21020 uses a modified Harvard memory architecture with two memory spaces: program memory (PM) and data memory (DM), each with its own address and data buses. The ADSP-21020 has no on-chip memory. However, it does include a 32-word on-chip instruction cache. The separate address and data buses for program memory and data memory are both brought off-chip. If both sets of buses are connected to physically separate memories, then the ADSP-21020 can in general complete one instruction fetch and one data memory access per instruction cycle.

When an instruction that attempts to perform two data memory accesses is executed for the first time, the second (PM) data memory access conflicts with fetching of the next instruction. When this occurs, the next instruction is stored in the cache, allowing subsequent executions of the dual-move instruction to execute in a single cycle. Thus, if the following instruction is contained in the cache, the processor can complete two data memory accesses in a single instruction cycle.

As of March, 1997, the 33-MIPS ADSP-21020 sold for $159.00 in quantity 1,000. All versions use a 223-pin PGA package. According to Analog Devices, a radiation-hardened version of the ADSP-21020 is under development by TEMIC of France.

A complete analysis of the ADSP-21020's successor, the ADSP-2106x family, including BDTI Benchmark™ results, is contained in BDTI's report, Buyer's Guide to DSP Processors, 2001 Edition.