BDTI’s DSP Insider Archives
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This month:
TI Demonstrates 1GHz ’C64xxOn May 5th, TI announced that it had demonstrated a ’C64xx chip running at 1GHz. TI did not announce any ’C64xx products at this clock speed, but indicated that it expects to be sampling such chips in the first half of next year. (The fastest ’C64xx devices currently available run at 720 MHz.) The new TI chips will target signal-processing intensive applications such as communications infrastructure equipment and high-definition video systems. TI’s demo is intended to give its customers confidence that the company can deliver next year on its promise of 1 GHz chips—a move likely intended to counteract skepticism resulting from TI’s (and other vendors’) past difficulties in achieving advertised speeds. The demo may also serve to refocus media attention on TI’s products following Analog Devices’ recent announcement of a 600 MHz Blackfin chip. Current 720 MHz ’C64xx chips are fabricated in a 0.13-micron process, while the new gigahertz chips will use a cutting-edge 90-nanometer process. This migration will make TI one of the earliest adopters of the new process generation. At 720 MHz, BDTI’s benchmarks show that the ’C64xx is the fastest mainstream DSP processor currently available—nearly twice as fast as, for example, the new 600 MHz Blackfin. At 1 GHz, the new ’C64xx chips will be about 40% faster than earlier family members, which will almost certainly enable TI to keep the title of fastest mainstream DSP nicely in hand.
You don’t have to look much beyond mainstream DSP processors, however,
to find faster chips. Intrinsity is already sampling a 2 GHz chip that
can easily best a 1 GHz ’C64xx (see the May 2003 edition of the DSP
Insider). And BDTI’s recent benchmarking of DSP-enhanced FPGAs—such
as Altera’s Stratix—indicates that even a low-end DSP-enhanced FPGA
would be much faster in some applications than the ’C64xx, regardless
of the ’C64xx’s planned clock speed increase. But neither of these
competitors has the impressive support infrastructure and broad market
acceptance that are integral to TI’s appeal.
BOPS Assets Rumored Acquired by AlteraThe one-line statement, “BOPS Inc. has ceased operations,” is all that remains at www.BOPS.com. Although there was no formal announcement of BOPS’s demise, the company’s closure has been common knowledge for some months (see the November 2002 edition of the DSP Insider). In an interesting development, recent reports—as yet unconfirmed—suggest that BOPS’ assets, including its extensive patent portfolio, have been acquired by FPGA giant Altera. Altera has not announced any such acquisition and, when asked, the company declined to comment. Such an acquisition would not be completely surprising. Altera, like its primary competitor, Xilinx, has focused significant attention in recent years on adding DSP-oriented architecture features to its FPGAs and on building up the associated development infrastructure. In addition to DSP-oriented architecture features such as fixed-function multipliers and distributed memory blocks, both Altera and Xilinx already offer embedded processor cores in their FPGAs. Altera emphasizes its home-grown “Nios” processor, offered as a soft core; Xilinx emphasizes the PowerPC, offered as a hard core embedded alongside the FPGA fabric. Both of these cores are general-purpose processors, intended to handle control tasks while the rest of the FPGA handles parallelizable DSP algorithms, for example. In addition, Altera has in recent months been promoting its “Code: DSP” initiative, a methodology for implementing DSP applications by using the Nios core in combination with DSP coprocessors built using the FPGA fabric.
One possible motivation for Altera to buy the BOPS assets is a desire
to embed a BOPS ManArray DSP core in Altera FPGA products. But a more
likely motivation is stockpiling DSP-processor-related patents as a
weapon in future patent conflicts. As Altera and its ilk increasingly
move into applications and architectures that were formerly the
exclusive domain of DSP processor vendors, conflicts over intellectual
property rights are to be expected. Acquiring BOPS patents and
assets, if indeed Altera has done so, may help the company come out on
the winning side of such future conflicts.
BDTI Case Study
This Month: Creating Top-Notch Tools for Signal ProcessingSignal processing has become an increasingly important component in a broad range of embedded systems. As a result, many embedded processors that were not originally designed with the needs of DSP in mind are now taking on DSP workloads. Unfortunately, even if the processor itself is up to the task, in many cases the processor’ software development tools are not. The tool features required by signal-processing software developers overlap with the features required by other types of embedded software developers, but there are some critical differences. One such difference is the need to support data visualization features, such as eye diagrams, constellation diagrams, and scope plots. Data visualization is extremely useful for debugging signal processing software, but is rarely used in developing other types of embedded software. In addition, unlike many other kinds of embedded software, signal processing software typically requires aggressive optimization to meet speed and memory-usage constraints. Processor tool chains should be designed to effectively support this effort. Perhaps most important is to provide good support for software profiling. Profiling allows programmers to identify the processing-intensive sections of their code, often called “hot spots” and to understand their cycle-by-cycle timing. Without good profiling tools, the programmer is often left guessing why the code runs longer than expected, and how it can be effectively optimized. This can be a serious problem for the DSP software developer, particularly if the processor has dynamic features (such as superscalar execution, caches, or branch prediction) that make it difficult to determine cycle counts by hand. A number of major processor vendors have engaged BDTI to help them improve their tools for signal-processing software development. In some cases, BDTI has identified critical new tools and specified their key features. In other cases, BDTI has performed in-depth evaluations of existing tools, providing detailed suggestions for improvement. BDTI’s strong background in both DSP software development and DSP tools evaluation puts it in a unique position to help companies create top-notch tools for developers of signal-processing software.
To learn more about how BDTI can help your company field tools that
give you a competitive advantage among signal processing application
developers, contact Jeremy Giddings at +1 510 665 1600 or
giddings@BDTI.com.
Impulse Response, by Jeff Bier
Gate Counts Don’t CountEvery so often I get a call from someone who wants to know the gate count (or equivalently, the silicon area) of some embedded processor core. And every time this happens, I have to stifle the urge to say “Why on earth do you care?” The reason the question baffles me is that, in chips that use embedded processor cores, the area used by the core is almost always negligible compared to the area eaten up by memory banks. It’s common for the processor core to consume only about 10% of the die area, with 60-80% consumed by memory. Thus, in typical embedded chips, the size of the core itself is just not that significant in determining overall chip size. “But wait,” you say. “Isn’t it important to choose a core that helps to minimize chip size (and hence cost)?” Absolutely. But comparing gate counts isn’t the best way to go about making this choice. A better metric to use for this purpose is processor memory efficiency. Memory efficiency measures how much memory is required for the core to execute a given task. It includes both program (instruction) and data memory. The core’s architecture and instruction set exert a direct influence on its memory efficiency; the quality of the compiler can also play a critical role if portions of the application are written in a high-level language. Because embedded chip size tends to be dominated by on-chip memory, the size of memory required by the core has a dramatic impact on the overall chip size—a greater impact than the size of the core itself. To illustrate this concept, imagine that Core A is 50% smaller than Core B, but uses 30% more memory. Assuming that with Core B the chip has an 8:1 ratio of memory area to core area, it turns out that the bigger core will yield a smaller chip. Of course, the chip designer can always skimp on memory to make the chip smaller, but then the system designer has to make up for it by adding off-chip memory banks. This can increase system cost and energy consumption and reduce system reliability.
As prospective core licensees become more aware of the importance of
memory usage, perhaps core vendors will spend less effort promoting
their svelte gate counts and more effort promoting the attributes that
really count.
New BDTI Seminar at Embedded Processor ForumThe 2003 Embedded Processor Forum, to be held June 16-19 at the Fairmont Hotel in San Jose, will feature a new BDTI seminar, Processors for Communication and Multimedia Applications. This seminar answers the question, “Which processors best meet the needs of the new, integrated communications and multimedia applications?” Today’s communications and multimedia applications, such as in smart phones and consumer media products, require serious signal-processing horsepower. But speed alone isn’t enough: processors for these applications must also provide rich development infrastructure and meet tight cost and power constraints. The seminar classifies the numerous processors that target communications and multimedia applications into manageable categories and provides in-depth, objective analysis of the most important architectures and products. The seminar reveals what it takes for a processor to succeed in today’s demanding DSP-centric applications and provides unique insights into technology trends and vendors’ strategies.
For information and links for schedule, location, and complete
program, go to http://www.BDTI.com/bdti_whatsnew.html#epf.
BDTI Products and Services
DSP Software Development ServicesBDTI overcomes difficult software implementation challenges, helping companies go to market with highly integrated and complex signal processing applications. For set-top boxes, multimedia-enabled cell phones, multimedia-enabled PDAs, Internet appliances, portable digital audio players, and more.
DSP Advisory ServicesBDTI helps companies make informed, solid decisions. BDTI can help: choose a new processor; select the right tools; evaluate a product plan; perform technical due-diligence; and more. From short-term consulting services to extensive research and analysis.
BDTI Technology ReportsCompanies use BDTI technology reports for insights into the technology choices and into their competitors. Based on hands-on benchmarking and in-depth analysis, BDTI’s Inside reports and Buyer’s Guide to DSP Processors deliver man-years of intelligent analysis and data.
You will find more information on these and other BDTI products and
services at http://www.BDTI.com. Or contact Jeremy Giddings at
giddings@BDTI.com.
BDTI Releases New PresentationsIf you missed BDTI’s workshops at ESC in San Francisco recently, you can view the slides online. Look for the following presentations from ESC:
Also look for these new presentations:
Go to http://www.bdti.com/articles/info_articles.htm#articles.
About BDTIBDTI is an independent source for DSP technology analysis and optimized DSP software development services. From rigorous technical analyses of processors for DSP, such as the Inside series of processor analyses, to highly regarded technology seminars, BDTI is the trusted independent source for reliable information on DSP technology. As a software developer, BDTI is known for highly optimized implementations of signal processing algorithms and applications and for solutions to complex problems of integration, code size, and performance.
For more information, visit our Web site at http://www.BDTI.com.
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