BDTI’s DSP Insider Archives
|
||
BDTI’s DSP Insider Archives |
|
|
| HOME << |
|
|
|
||
This month:
TI Expands Into Base Station ChipsetsToday, TI introduced two 3G chipsets, one for handsets and one for base stations. Although TI and other vendors have long offered handset chipsets, TI’s base station chipset is the first from a major semiconductor vendor. ASIC-plus-DSP designs dominate the base station market for a number of reasons, including high computational loads, power constraints, and cost pressures. Nonetheless, TI says the superior cost and performance of its chipset will enable it to displace ASIC-based designs. The chipset consists of a TCI100 DSP, a TC110 transmit ASSP, and a TC120 receive ASSP. The TCI100 is essentially a TMS320C6416, a processor used widely in today’s base station designs. The TCI100 is projected to operate at 720 MHz, 20% faster than the fastest ’C6416. The TC120 contains a pool of accelerators for spreading and other transmit functions. These accelerators can be allocated to channels as needed. Similarly, the TC110 contains pools of accelerators for de-spreading and other receive functions. In essence, these ASSPs are application-specific reconfigurable processors similar to those from MorphICs and PicoChip—companies that also target base stations. Base station-oriented reconfigurable processors have also received attention from Motorola, which recently invested in Morpho Technologies. According to TI, its chipset will offer up to twice the channel density of an ASIC-based design. TI says most of this gain comes from an efficient interface between the DSP and ASSPs. TI acknowledges that ASIC designers could implement a similar interface, but claims its intimate knowledge of the ’C64xx gives it a leg up in this area. The TI chipset also has an advantage in that it supports the recently finalized HSDCA standard, which enables higher data download rates for mobile data users. TI also says that its chipset will cost far less than ASIC-based designs. While this may be true, TI’s potential customers are likely to be more concerned about risk than about cost. Base stations are extraordinarily complex systems, and base station manufacturers have huge investments in their designs. Moving to TI’s chipset will require a massive porting effort, and this may slow acceptance of TI’s chipset just as it has slowed acceptance of solutions from vendors like MorphICs and PicoChip.
Moving from in-house designs to TI’s chipset will also increase
manufacturers’ dependence upon TI’s long-term road-map. Unlike the
start-ups that pioneered innovative base-station chip architectures,
TI is a large, established vendor with little risk of collapsing
overnight. Nevertheless, TI must convince its prospective customers
that it has a solid long-term strategy—and that it will execute that
strategy—before those customers will give its new chipset serious
consideration.
LSI’s Energy-Efficient LSI403LP Hits ProductionLast August, LSI Logic announced a new member of its LSI40x DSP processor chip family, the LSI403LP. The new chip targets cost- and power-sensitive applications, particularly audio and voice processing. LSI says that at 150 MHz and 1.2 volts the LSI403LP burns just 55 mW of power—an impressively low figure. According to LSI, the chip has now reached production and is available at 150 MHz for about $10 in 10K quantities. The LSI403LP is based on LSI’s ZSP400 DSP core, a superscalar, 16-bit fixed-point, dual-MAC architecture that is capable of executing up to four instructions in parallel. (The ZSP400 is the predecessor to LSI’s ZSP500, which was announced in September of 2002 and is not yet available in chip form.) In addition to being offered in off-the-shelf chips, the ZSP400 core is also available from LSI as licensable IP and as a building block for customer-designed SoCs fabricated by LSI. The core’s availability in these three forms is unique among DSP architectures and is a strong advantage. An OEM can start product development with an off-the-shelf LSI400 family chip, for example, and then migrate to a custom SoC when volumes justify the costs of a custom chip design. The LSI403LP’s main competitors are TI’s ’C55xx family and Analog Devices’ Blackfin (ADSP-2153x) family. The LSI403LP is not as fast as the fastest versions of these two competitors; at 150 MHz, it has a BDTImark2000™ score of 700, compared to a score of 1690 for the 300 MHz ADSP-21535 and 970 for the 200 MHz ’C5509. (Detailed benchmark results and analysis for the ZSP400 are available in two of BDTI’s reports, Buyer’s Guide to DSP Processors and Inside the LSI Logic ZSP500.)
The LSI403LP shines in terms of energy efficiency, however. At 150
MHz, its BDTImark2000/mW energy-efficiency score is 12.8. The ’21535
(operating in its reduced speed/reduced voltage mode) and the ’C5509
both have energy efficiency scores that are about half as good as that
of the LSI403LP; the ’21535’s result at full speed is even worse. The
LSI403LP’s energy-efficiency advantage may be short lived, however; a
forthcoming chip from ADI, the ’21532, is expected to close the gap
and offer similar energy efficiency. Until then, the LSI403LP will
enjoy a coveted spot as the most energy-efficient chip—by far—in
this field of competitors.
BDTI Case Study
This Month: Rapid PrototypingPrototyping a new product can provide a number of valuable benefits, such as gaining investors’ confidence and gauging customers’ needs. Because the time available for prototyping is usually short—often only a few weeks—prototyping efforts typically rely on quick assembly of off-the-shelf components. Unfortunately, this approach often breaks down for signal processing software. If the prototype incorporates new or unusual signal-processing features, there may not be off-the-shelf software that suits the prototype. Even when appropriate software is available, it may be necessary to modify that software. For example, code compiled from C may run too slowly to demonstrate the desired functionality, and it may be necessary to hand-optimize portions of the code. Finally, signal processing software presents unique integration challenges. For example, signal processing software often places heavy loads on chip- and system-level peripherals. Integration challenges are particularly great for the many processors that lack good system-test infrastructure. Addressing these challenges often requires a combination of skills. For example, creating new signal-processing software may require the prototype designer to consider several different algorithmic approaches, and the best approach may depend upon the processor being used. A deep understanding of both signal processing and processors is invaluable in such cases. Similarly, quickly optimizing existing software requires detailed knowledge of techniques that provide maximum speed-ups with minimum code changes. Whether the signal processing software is new or based on off-the-shelf components, quickly integrating the software requires expert knowledge of the software’s system-level behavior and experience in system-level troubleshooting and tools. BDTI can help with all of these challenges and more. With its years of experience developing signal processing software, BDTI can quickly meet challenging algorithm, performance, and integration goals. For example, BDTI was recently engaged to create optimized image-processing functions for a prototype product demonstration platform. Working with the customer within a three-week timeframe, BDTI specified the algorithms, co-designed an application programming interface, created a test infrastructure, and created, tested, and delivered optimized implementations of the functions.
For more information on how BDTI can help you quickly build a
prototype, contact Jeremy Giddings (giddings@BDTI.com), or visit
http://www.bdti.com/products/services_software.html.
Impulse Response, by Jeff Bier
Processor Architecture Still MattersConvergence was a clear theme among the most sophisticated products introduced at last month’s Consumer Electronics Show. One of the more intriguing examples was the Lyra Audio/Video Jukebox from RCA. This handheld device has a list of audio and video capabilities long enough to make a Swiss army knife jealous. Its list of hardware components is equally impressive: an internal hard drive, color LCD, and a bevy of connectivity options are only the beginning. This long list of components begs the question: how important is the processor when it has so many expensive and power-hungry neighbors? If, for example, a huge internal hard drive dominates system costs, why bother finessing the perfect balance of processor price and performance? Just pick a processor that gets the job done and move on. Before making this leap, however, system designers should consider the nature of the software development effort they face. For mature markets, many consumer products are built around highly integrated, off-the-shelf solutions that include both the processor and required media-processing software. In this scenario, most of the custom-developed software—a user interface, for example—is not computationally intensive and is likely to be written in C or C++. For this type of software, the architectural details of the processor make little difference. On the other hand, cutting-edge consumer electronics products by their nature cannot rely on pre-packaged, off-the-shelf solutions. Often, media-processing software needed for the cutting-edge features must be created by the system developer. In such cases, the choice of processor matters greatly. Although compilers have come a long way, it’s still virtually impossible to wring competitive media-processing performance out of a processor without an intimate knowledge of processor’s architectural details. Thus, the ease of developing media-processing software depends greatly on the processor architecture.
Over the last few years, embedded processors of all types have been
promoted for media-processing applications. But make no mistake:
shoehorning advanced media-processing software onto a poorly suited
architecture is like pounding a square peg into a round hole. It can
be done, but it requires a big hammer... and the results aren’t
pretty.
Join BDTI at GSPx/ISPC — March 31-April 3, 2003Join BDTI at the Global Signal Processing Expo (GSPx) and International Signal Processing Conference (ISPC), a new conference and industry event that will provide a forum for peer-to-peer interaction among engineers and managers who create and use signal processing technology. BDTI General Manager Jeff Bier will lead a panel discussion on the critical topic, “The Future of DSP Engineering.” Jeff has assembled an outstanding panel of experts from the tools, chips, systems, and academic communities. The panelists will explore the key challenges that will be faced by developers and users of DSP technology in the coming years, and what must be done to meet these challenges. BDTI will also present two papers, “DSP Benchmarks for the Latest Processors” and “Evaluating FPGAs for Communications Infrastructure Applications.” “DSP Benchmarks” will include the results for several new processors, including TI’s OMAP and the Intel XScale. “Evaluating FPGAs” will provide important insights into the strengths and weaknesses of DSP-enhanced FPGAs for signal processing applications—including the first-ever independent DSP benchmarks for FPGAs.
GSPx/ICSP will be held at the Hotel Intercontinental in Dallas, Texas,
from March 31 to April 3, 2003. More information on the event and BDTI
participation is available at
http://www.BDTI.com/bdti_whatsnew.html#gspx.
BDTI Organizes Consumer Electronics Track at Embedded SystemsThe Embedded Systems Conference (ESC), the most comprehensive event for the embedded industry, combines exhibition, business events, and technical conferences and provides a first look at the latest technologies in the world of electronics. This year, BDTI has organized a new Consumer Electronics track for ESC, featuring panel discussions and classes that will provide unique independent perspectives and in-depth insights for engineers, marketers, and managers. The panel discussion, “Key Challenges for Consumer Media Products,” will bring together diverse viewpoints from content providers, home entertainment equipment manufacturers, and consumer advocates in a frank discussion of the challenges impeding the widespread adoption of new consumer media technology.
In addition, BDTI will present four in-depth classes at ESC. For more
information, go to http://www.bdti.com/bdti_whatsnew.html#esc and
click on the “ESC 2003” link.
BDTI Products and ServicesAre you aware of these BDTI products and services?
You will find more information on these and other BDTI products and
services at http://www.BDTI.com. Or contact Jeremy Giddings at
giddings@BDTI.com.
About BDTIBDTI is an independent source for DSP technology analysis and optimized DSP software. From rigorous technical analyses of processors for DSP, such as the Inside series of processor analyses, to highly regarded technology training classes, BDTI is the trusted independent source for reliable information on DSP technology.
For more information, visit our Web site at http://www.BDTI.com.
The next issue of BDTI’s DSP Insider is coming in March. Previous issues of BDTI’s DSP Insider are archived on BDTI’s Web site. Follow the link from http://www.BDTI.com/dspinsider.htm. If you have comments, suggestions, or other feedback about the DSP Insider, please send email to dspinsider@BDTI.com. BDTI’s DSP Insider is a free monthly electronic newsletter published by Berkeley Design Technology, Inc. If our newsletter was forwarded to you and you would like to receive it regularly, please register at http://www.BDTI.com/dspinsider.htm.
If you no longer wish to receive the DSP Insider send an email
message to dspinsider@BDTI.com with the words “Remove me” in the
subject line.
BDTI’s DSP Insider © 2003 Berkeley Design Technology, Inc. |