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Vol. III, No. 1 BDTI’s DSP Insider January 2003

This month:


TI Boosts Speed, Cuts Costs of ’C55xx DSPs

Last month Texas Instruments announced two new members of its ’C55xx family, the TMS320VC5501 and the TMS320VC5502. At a projected clock speed of 300 MHz, these new chips will bring the speed of the ’C55xx family—which currently tops out at 200 MHz—more in line with that of its main competitor, Analog Devices’ ADSP-2153x “Blackfin” family. BDTI’s analysis shows that at the projected clock speed of 300 MHz, the new ’C55xx chips will be about 15% slower on typical DSP tasks than the currently shipping 300 MHz ADSP-21535. BDTI’s analysis also shows that in terms of speed, a 300 MHz ’C55xx will lie halfway between the slowest and fastest ’C62xx family members (the 150 MHz ’C6211B and the 300 MHz ’C6202B, respectively). In contrast, a 200 MHz ’C55xx barely nudges past the slowest ’C62xx. (Benchmark scores for the processors discussed in this article are available at http://www.BDTI.com/bdtimark/BDTImark2000.htm.)

Despite their higher speeds, the new ’C55xx family members will cost much less than existing family members. For example, the 300 MHz ’C5501 will cost only one-third as much as the family’s current price leader, the 144 MHz ’C5509. The new chips achieve their low prices mainly by minimizing on-chip memory. For example, the ’C5501 contains only 48 KB of memory, compared to 256 KB on the ’C5509. Even considering the small on-chip memories, though, the new chips significantly improve the cost-performance ratio of TI’s low-cost offerings. For example, an 80 MHz ’C5402 costs as much as a 300 MHz ’C5501, but the ’C5501 offers roughly six times more speed and three times more on-chip memory than the aging ’C5402.

Looking beyond TI’s offerings, the ’C5502 bears a striking resemblance to ADI’s forthcoming ADSP-21532. Both chips will achieve similar signal-processing speeds; both will contain 80 KB of memory; both will be priced at $9.95 in 10,000-unit quantities; and both are expected to begin sampling in the first quarter of 2003.

According to TI, the new ’C55xx chips will be slightly more energy-efficient during normal operation than existing family members. However, the new chips will have somewhat higher idle-mode power consumption than existing ’C55xx family members. In addition, the new chips contain far less on-chip memory than existing ’C55xx family members, which means that applications using the new ’C55xx chips are more likely to require off-chip memory accesses. Idle-mode power consumption and off-chip memory accesses are two of the largest contributors to overall energy use in many applications, so comparing the energy-efficiency of the ’C5501 and ’C5502 to that of existing family members will require a careful, application-specific analysis.

According to TI, the ’C5502 will begin sampling in the first quarter of 2003. The 300 MHz version will be priced at $9.95. A 200 MHz version will also be available, priced at $7.95. The 300 MHz ’C5501 will begin sampling in the third quarter of 2003, and will be priced at $5.00. (All prices are for 10,000-unit quantities.)

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ADI Ships 300 MHz TigerSHARC

On December 16th Analog Devices announced a new member of its high-performance fixed-/floating-point TigerSHARC family, the ADSP-TS101S. The chip runs at 300 MHz in a 0.13-micron process and is already in full production at this speed, according to ADI. The ADSP-TS101S is intended for high-performance multiprocessor applications, including telecommunications infrastructure, medical imaging, industrial instrumentation, and military electronics.

BDTI has not yet benchmarked TigerSHARC, but based on analysis of its architecture, it is likely that at 300 MHz the ADSP-TS101S is the fastest floating-point DSP available. The only real competitor among floating-point DSPs is Texas Instruments’ TMS320C67xx, which is currently in production at 167 MHz and sampling at 225 MHz. At 300 MHz, TigerSHARC’s fixed-point DSP performance is likely to be in the same league as that of TI’s flagship fixed-point architecture, the 600 MHz TMS320C64xx.

TigerSHARC’s performance doesn’t come cheap, though; the 300 MHz ADSP-TS101S is priced at $199 in 10,000-unit quantities, making it one of the most expensive DSP processors on the market. ADI believes that the chip’s hefty price tag is justified by its large on-chip memory and specialized I/O support for multiprocessor systems.

Announcing a chip that’s already available at its target clock speed is a significant (and welcome) change from ADI’s earlier policy of announcing chips far in advance of their availability. Indeed, when ADI first introduced TigerSHARC in 1998, the company announced its clock speed as 250 MHz—a speed that ADI didn’t deliver until early 2002 (see the May 2002 DSP Insider at http://www.bdti.com/dspinsider/archives/dspinsider_020501.html).

In the years that have elapsed since TigerSHARC was first introduced, the long-term outlook for high-performance floating-point DSPs has become somewhat murky. High-performance DSP-enhanced general-purpose processors—most prominently the PowerPC 74xx family—have begun to encroach on this market. It is notable that TI has not yet announced a floating-point counterpart to its top-of-the-line, fixed-point ’C64xx architecture, as the company did a few years back when it announced the floating-point variant (’C67xx) of its ’C62xx architecture. It will be interesting to see how TigerSHARC competes against the MPC74xx, and whether TI ups the ante with a new floating-point DSP architecture of its own.

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BDTI Case Study

This Month: Polynomial Approximations: A Powerful Tool

Last month, we examined common sources of computation error found in DSP applications. One of these sources of error arises from the need to approximate non-linear mathematical functions such as sin(x) and log(x). While processors can easily produce sufficiently accurate results for basic functions like addition and multiplication, computing non-linear functions with sufficient accuracy is not straightforward. Typically, approximations are used. Choosing the appropriate approximation requires careful consideration of trade-offs between accuracy, speed, memory use, and development complexity.

Look-up tables are one approach to approximating non-linear functions. Look-up table techniques are easy to implement and fast to execute, but are memory-hungry, due to their reliance on tables stored in memory. The size of the tables may range from hundreds to thousand of words, depending on the error that can be tolerated by the application—and each function may need its own table.

Another approach is the use of a polynomial approximation, where intermediate terms are computed based on the input argument and are combined to generate a result that approximates the true result. Polynomial approximations generally have longer execution times than table lookup approaches, but use far less memory—ten words or less of storage for the polynomial coefficients is not uncommon.

However, the design and implementation of polynomial approximations is not without potential pitfalls. If the design requirements of the approximation cannot be met with a textbook polynomial, a new polynomial must be developed. Development of a polynomial with the desired properties is difficult and time consuming compared to the development of a lookup table. The principal difficulty lies in balancing error performance, accuracy, and execution time. For example, improving error performance and accuracy typically requires a more complex polynomial design, but a more complex polynomial design results in longer execution times. It may be possible to design a less complex polynomial that meets design requirements—but this will generally require a greater design and development effort.

BDTI has created a set of in-house proprietary tools for use in BDTI’s DSP application software services business. These tools allow rapid creation of polynomial approximations that have the desired error performance while minimizing execution time and memory use. BDTI’s tools also allow the creation of hybrid approximations that combine the simplicity of table lookup with the accuracy and low memory requirements of polynomial approximations. For example, BDTI has used these tools successfully in audio software projects where accurate and fast computation of non-linear functions was required as part of an optimized software implementation.

More information on BDTI’s DSP application software development services may be found at http://www.bdti.com/products/services_software.html. To find out how BDTI can help you with your DSP software development needs, please contact Jeremy Giddings at BDTI (giddings@BDTI.com).

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Impulse Response, by Jeff Bier

Processor Designers’ Sad, Sad World

Stroll the halls of any computer engineering graduate school and you will doubtless encounter numerous students brimming with ideas for cranking up processor speeds. Until recently, graduates of these schools found a warm welcome in the PC processor market, which seemed to have an insatiable need for speed. Today, however, fewer and fewer PC buyers are willing to pay a premium for more speed—after all, who needs a 3 GHz processor to write a letter to Grandma? If the PC market no longer needs ever-faster processors, perhaps these computer engineering students should have majored in art history instead.

In reality, computer architecture grad students need not worry. While the lust for ever-faster PC processors may be waning, communications applications still have a nigh-limitless demand for computational horsepower. Communications applications are constrained by inherently limited resources, which creates strong economic incentives to use these resources efficiently. For example, there is a limited amount of radio spectrum, so squeezing twice as many users onto the same amount of spectrum is extremely valuable. Fortunately for the up-and-coming processor architect, this need for efficiency translates directly into a need for processing power. For example, more-efficient radio spectrum use can be obtained via more-sophisticated—and hence computationally intensive—modulation, coding, and compression techniques.

Alas, the signal-processing work at the heart of communications applications has little in common with typical PC applications. As a result, the standard bag of tricks employed to improve PC speeds—deep pipelines, complicated branch prediction schemes, and the like—are not appropriate for communications applications. Worse yet, communications applications demand enormous processing power on shoestring budgets. While PC processors command multi-hundred-dollar prices, communications applications typically impose low-double-digit budgets on the processor. And while PC processors often consume dozens of watts of power, most communications processors are stuck with power budgets of a mere fraction of a watt.

The good news for processor designers is that there is much challenging work still to be done. The bad news is that the new challenges are quite different from the old. At least processor designers don’t have to fall back on that interest in art history.

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Register for GSPx/ISPC — March 31-April 3, 2003

The International Signal Processing Conference (ISPC) and Global Signal Processing Expo (GSPx) will provide a forum for peer-to-peer interaction among engineers and managers who create and use signal processing technology. This new conference and trade show is organized by Amnon Aliphas, the founder of ICSPAT/DSP World, and will be held at the Hotel Intercontinental in Dallas, Texas, from March 31 to April 3, 2003.

ISPC will combine workshops and conference presentations with panel sessions led by industry leaders on compelling topics that impact the direction of DSP technology. GSPx will provide a venue for companies to introduce and demonstrate new technologies and products.

More information on GSPx and ISPC is available on the GSPx Web site at http://www.gspx.com/ISPC/index.html. Registration for the conference is now open at
http://www.gt-conferences.com/ISPC/register.html.

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Improved “Sounding Board” Service for Marketing Presentations

In these times, it is more important than ever to make sure your marketing presentation is technically correct and accurately targeted. BDTI’s “Sounding Board” service helps vendors of DSP-related products—chips, cores, tools, and software—develop accurate and compelling marketing presentations.

BDTI has improved the Sounding Board service by enhancing procedures before, during, and after the session which are designed to make sure that key issues are highlighted early, time is used efficiently, and feedback is prioritized and tailored to your needs. The result is more usable information for you.

For more information, go to http://www.bdti.com/products/services_sounding.html, or contact Jeremy Giddings at giddings@BDTI.com.

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Latest Technology Analysis Reports from BDTI

Inside the LSI Logic ZSP500

Inside the LSI Logic ZSP500 provides a comprehensive qualitative analysis of the processor architecture and features, along with a complete quantitative performance analysis based on the BDTI Benchmarks™.

http://www.BDTI.com/products/reports_zsp500.html.

FPGAs for DSP

FPGAs for DSP provides a detailed assessment of the DSP capabilities of DSP-capable FPGAs and explains why FPGAs are a compelling solution for some DSP applications. The report discusses new offerings from Altera and Xilinx and includes benchmark results of FPGA DSP performance.

http://www.BDTI.com/products/reports_focus.html

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About BDTI

BDTI is an independent source for DSP technology analysis and optimized DSP software. From rigorous technical analyses of processors for DSP, such as the Inside series of processor analyses, to highly regarded technology training classes, BDTI is the trusted independent source for reliable information on DSP technology.

For more information, visit our Web site at http://www.BDTI.com.

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