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This month:
BOPS Quietly Calls it QuitsBOPS, Inc. quietly began auctioning off its patent portfolio last month, signaling the end of its operations as a vendor of high performance licensable DSP cores. Given the current business climate, the failure of another licensable core vendor is hardly surprising. (For more examples, see our story on Lexra in the February edition: http://www.bdti.com/dspinsider/archives/dspinsider_020201.html.) However, BOPS had a few things working against it beyond the industry slow-down. The BOPS architecture was based on a complicated, scalable array of powerful processing elements. At its 1997 introduction, this design was much faster than those offered by established processor and licensable core vendors. A 2 × 2 array of these elements, for example, could easily outperform the fastest mainstream DSPs of the day. BOPS initially targeted this architecture at the “media processor” market, along with companies like Chromatic, MicroUnity, and Philips. These companies fielded high-performance VLIW architectures targeting multimedia-intensive applications. But the media processor market has been slow to develop, and media processor vendors have had difficulty finding volume applications for their architectures. Later, BOPS repositioned its architecture as a licensable core for a wider range of signal processing applications, including voice-over-IP and wireless LANs. When BOPS hired Carl Schlachte as its CEO in 2000, much was made of his earlier tenure at ARM, Inc. Indeed, it was largely ARM’s success—coupled with the ready availability of venture capital—that attracted companies like BOPS to the processor core licensing business in the late 90’s. But while ARM cores focused on simplicity and low cost, BOPS targeted high performance with a complex architecture. Much like the media processor market, the market for high-performance licensable cores has yet to emerge. Licensable cores are used in custom chips, which in turn are used mainly in high-volume applications. Because such applications tend to be extremely cost-sensitive, core licensees typically seek the smallest, simplest core that can get the job done—in short, the opposite of BOPS’ architecture. Hence, BOPS’ combination of a high-performance architecture and an IP-licensing business model severely limited its potential customer base.
The BOPS architecture was an impressive technical achievement. But
with only two licensees announced over the course of the company’s
five-year history, BOPS’ demise may prompt other licensors of
high-performance processor cores, such as TriMedia and Siroyan, to
reconsider their strategies.
Embedded DRAM Comes of AgeSeveral vendors recently unveiled embedded processors containing large amounts of on-chip RAM—but not the SRAM usually found in embedded processor chips. Instead, these new processors integrate copious quantities of on-chip DRAM. Embedding DRAM with processing logic can greatly improve on-chip memory bandwidth by providing access to the wide internal bus structures present in DRAM. Combining embedded DRAM (eDRAM) with processing logic also creates an opportunity to choose between cost and performance. By fabricating the chip in a memory process, chip designers can achieve high memory densities—and hence lower chip costs—at the expense of lower speeds. Alternatively, designers can use a logic process to achieve high clock rates at the expense of reduced density and higher chip costs. One example of the emerging eDRAM trend is Toshiba’s new TMPR9961 processor, which contains an 800 MHz MIPS64 core, 32 MB of logic process eDRAM, and a host of I/O interfaces (USB, DDR, etc.). The TMPR9961 targets graphics-oriented embedded applications like automotive navigation systems, set-top-boxes, and digital televisions. The eDRAM is used exclusively as video memory; the caches for the MIPS core use conventional SRAM. (Toshiba says future versions of the chip will implement the caches with eDRAM.) Toshiba claims that the eDRAM allows the TMPR9961 to achieve greatly improved pixel fill-rate performance compared to an off-chip DRAM configuration.
Memory giant Micron recently bolstered the argument for eDRAM with the
announcement of its first processor. This processor, code-named
Yukon, contains an array of 256 8-bit integer ALUs and
As memory-intensive embedded applications like video processing
continue to proliferate, eDRAM will likely gain increasing attention.
Indeed, the new processors from Toshiba and Micron suggest that the
embedded DRAM concept may have come of age.
BDTI Case Study
This Month: Uncovering Software Performance BottlenecksIt is often easy to tell when DSP software is not meeting its performance goals—an audio output may stutter, for example. But to efficiently improve software performance, developers need to know which portions of the software are consuming the bulk of the processor’s time, and why. To help developers examine software performance, processors often include “event counters” that track performance-related events such as data cache misses and branch mispredictions. In some processors, these counters provide all the data needed to identify the sources of slowdowns. Unfortunately, most processors have limited event-tracking capabilities. For example, while some processors can track dozens of types of cache events, others only indicate that the cache caused a stall, leaving the programmer to figure out the cause. Even when a processor provides plenty of performance data, accessing this data can be difficult. For example, many processors only permit access to performance counters when the processor is in a special operating mode. In addition, the documentation for performance-tracking features is often insufficient or incorrect. Fortunately, there are ways to measure performance even when the processor provides little performance data. For example, if a developer suspects that data cache misses are causing slowdowns, the developer can temporarily modify the software so that it always accesses the same data. This eliminates most data cache misses, allowing the developer to estimate how much performance was being lost to cache misses. Although such workarounds can provide critical performance data, they are time-consuming to implement. To implement these workarounds efficiently, a designer needs to know where to look for slowdowns ahead of time. This requires a thorough understanding of both the application and the processor. With its expertise in optimizing DSP application software and experience with a broad range of processors, BDTI is particularly well equipped to take on this challenge. In one recent example, BDTI was asked to implement a streaming media application on a processor with extremely limited performance-tracking capabilities. Using its understanding of the application and of the processor’s cache, BDTI deduced that a small section of the application was causing a large number of cache misses and designed a test that confirmed this hypothesis. This allowed BDTI to focus its optimization efforts and achieve a significant speed-up with minimal code changes.
To learn more about how BDTI can help you optimize your DSP
applications, contact Jeremy Giddings (giddings@BDTI.com) or visit
http://www.bdti.com/products/services_software.html.
Special Feature: Guest Editorial
Japan Semiconductor TrendsCopyright InsideChips.com 2002Until fairly recently, Japan was the largest semiconductor market in the world. In 1989, the Japanese market represented about 40% of total worldwide chip sales. However, the latest Semiconductor Industry Association forecast shows that the Japanese market was only 24% of the total in 2001 and will decline to 19% in 2005. Although Japan’s semiconductor market share is declining, semiconductor vendors still need a good strategy for Japan. One reason for the decline in Japanese semiconductor consumption is declining that OEMs are shifting volume production to other Asian countries. We believe Japanese companies will preserve their dominance in digital consumer-electronics products, but will produce a larger percentage of their products in lower-cost Asia-Pacific countries. Chip suppliers that want to expand their business in the growing Asia-Pacific market should acquire design-ins in Japan, as these design-ins will migrate to offshore Asian plants. U.S. semiconductor vendors typically obtain only 8% to 13% of their business from Japan. Although chip-related trade conflicts between Japan and the U.S. are history, U.S. chip firms still face big challenges in Japan. For example, Japanese OEMs are requesting detailed information on chip vendors’ procedures for minimizing the environmental impact of their products. These requests are difficult to fulfill, especially for smaller vendors. To succeed in Japan, chip vendors must customize their marketing and sales strategies for the Japanese market. Two key factors are tapping the right manager for the firm’s Japanese branch office and selecting the appropriate local distributors and partners. We have observed U.S. companies make many mistakes in setting up operations in Japan. For example, U.S. companies often assume a person with good English skills and respectable credentials would make a good Japanese branch manager. However, this is not a good strategy unless the candidate has an established reputation in Japan. New managers often make policy changes or reorganizations that result in key sales staff quitting or unmotivated distributors. A better choice for a branch manager is an up-and-coming Japanese national who has worked for another American firm in Japan and has experience in the chip business. In Japan, no semiconductor distributors dominate the market as Avnet and Arrow do in the United States. Chip vendors can choose from 50 distributors that specialize in selling and marketing foreign-made semiconductors. In addition, some “captive distributors” that traditionally sold products of only one Japanese supplier are now aggressively seeking new business opportunities by selling foreign products. The Japanese semiconductor industry is in a major transition. Hitachi and Mitsubishi will consolidate their semiconductor businesses, and NEC is spinning off its chip business. Toshiba and Fujitsu have announced a strategic alliance of their SOC businesses and may establish a joint venture in the near future. We predict other major Japanese semiconductor suppliers, such as Matsushita, Sharp, and Sony, may tie up with one of the big-three groups mentioned above. We believe these changes provide business opportunities because many product-development plans will be delayed during this transition. In light of the new opportunities presented by these structural changes, we recommend chip firms review their Japanese strategies.
About the AuthorSteve Szirom is President of InsideChips.com, where he manages market studies, technology assessment, and semiconductor economic analysis. Mr. Szirom has provided management consulting to start-ups, venture companies, and overseas firms, and is a regular columnist for several semiconductor industry publications.
InsideChips (http://www.insidechips.com) provides business and
marketing information and analysis to the semiconductor industry, with
a focus on emerging startups. The company’s offerings include
InsideChips.com, an online repository of semiconductor market
research, market forecasts, and financial information, and
InsideChips.Ventures, a monthly print- and Internet-based report on
emerging semiconductor companies and technologies.
Join BDTI in Supporting GSPx/ISPCFinally, a conference and expo aimed at signal processing applications and engineers! The International Signal Processing Conference (ISPC) and Global Signal Processing Expo (GSPx) will provide a forum for peer-to-peer interaction among engineers and managers who create and use signal processing technology. This new trade show and conference is organized by Amnon Aliphas, the founder of ICSPAT/DSP World, and will be held at the Hotel Intercontinental in Dallas, Texas, from March 31 to April 3, 2003. The technical conference will combine workshops and conference presentations with panel sessions led by industry leaders on compelling topics that impact the direction of DSP technology. The expo will provide a venue for companies to introduce and demonstrate new technologies and products.
More information on GSPx and ISPC is available on the GSPx Web site at
http://www.gspx.com/ISPC/index.html.
BDTI Communications Benchmark™ (OFDM)The first of BDTI’s DSP Application Benchmarks™ is available for licensing. The BDTI Communications Benchmark (OFDM) models an OFDM (orthogonal frequency division multiplexing) receiver, which is used in a variety of communications applications, such as fixed wireless systems. This new benchmark can be applied to a range of processor technologies, including DSPs and FPGAs; results for Altera’s Stratix FPGAs and Motorola’s SC140-based MSC8101 are published in BDTI’s new report FPGAs for DSP. To ensure fair comparisons, BDTI’s specification details key benchmark parameters such as sample rates, filter lengths, and channel-code constraint lengths. BDTI certifies benchmark implementations before publication of results.
http://www.bdti.com/products/services_benchmarking.html#app_benchmarks
BDTI Technical Reports
Inside the LSI Logic ZSP500A new addition to the Inside series, this report on the LSI Logic ZSP500 provides a comprehensive qualitative analysis of the processor architecture and features, along with a complete quantitative performance analysis based on the BDTI Benchmarks™. For a free summary, see http://www.BDTI.com/articles/zsp500_summary_report.pdf. For info on the full report, go to http://www.BDTI.com/products/reports_zsp500.html.
FPGAs for DSPFPGAs for DSP provides a detailed assessment of the DSP capabilities of DSP-capable FPGAs and explains why FPGAs are a compelling solution for some DSP applications. The report discusses new offerings from Altera and Xilinx and includes benchmark results of FPGA DSP performance. http://www.BDTI.com/products/reports_focus.html
Inside the ARM ARM7, ARM9, and ARM9EBDTI’s Inside report on the most widely licensed microprocessor cores provides detailed analysis of these cores’ capabilities for signal processing applications, including benchmark results and comparisons with other widely used processors such as the Hitachi SH3-DSP, Motorola DSP5685x, TI ’C54, and TI ’C55.
http://www.BDTI.com/products/reports_arm.html
BDTI WebcastJeff Bier joins TI’s Ray Simar and EE Times’ Steve Ohr in a panel discussion, “So Many Architectures, So Little Time: Difficult Choices for Signal Processing.” Jeff and Ray will discuss the trade-offs between cost, performance, power consumption, and time-to-market that drive choices among FPGAs, DSPs, microprocessors, and ASSPs.
Thurs, Nov. 21, 2002; 10:00 a.m. PST/Noon CST About BDTIBDTI is an independent source for DSP technology analysis and optimized DSP software. From rigorous technical analyses of processors for DSP, such as the Inside series of processor analyses, to highly regarded technology training classes, BDTI is the trusted independent source for reliable information on DSP technology.
For more information, visit our Web site at http://www.BDTI.com.
The next issue of BDTI’s DSP Insider is coming in December. Previous issues of BDTI’s DSP Insider are archived on BDTI’s Web site. Follow the link from http://www.BDTI.com/dspinsider.htm. If you have comments, suggestions, or other feedback about the DSP Insider, please send email to dspinsider@BDTI.com. BDTI’s DSP Insider is a free monthly electronic newsletter published by Berkeley Design Technology, Inc. If our newsletter was forwarded to you and you would like to receive it regularly, please register at http://www.BDTI.com/dspinsider.htm.
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