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This month:
The ZSP500: Flexibility = SpeedLast week LSI Logic introduced the ZSP500, the latest member of its ZSP family of superscalar DSP cores. The ZSP500 is a dual-MAC processor, but BDTI’s analysis shows that at a projected clock speed of 325 MHz, the ZSP500 will be faster on DSP tasks than many other dual-MAC processors. For example, the ZSP500 will be faster than existing members of Texas Instruments’ TMS320C55xx family or Analog Devices’ ADSP-2153x family. The ZSP500 will even outpace some quad-MAC processors like 3DSP’s SP-5. (Benchmark results for all of these processors are available at http://www.BDTI.com/bdtimark/BDTImark2000.htm.) The ZSP500 owes much of its impressive speed to its flexible approach to parallelism. Typical mid-range DSPs—the TMS320C55xx, for example—can execute only two instructions in parallel. These processors achieve much of their parallelism by specifying multiple operations within each instruction. This approach offers limited flexibility because instruction sets include only select combinations of operations. In contrast, the ZSP500 uses simple instructions—each of which generally specifies a single operation—and achieves its parallelism by issuing up to four instructions per clock cycle. This approach allows more flexibility in selecting operations for parallel execution. Such flexibility is particularly important for “housekeeping” operations like initializing address registers. Housekeeping operations appear in a wide range of fairly arbitrary combinations, but it is only practical to include a few common combinations in an instruction set. Hence, it is often easier to execute housekeeping operations in parallel on the ZSP500 than on other mid-range DSPs. This is an important advantage: housekeeping tasks account for a significant portion of the workload in many applications, and the portion of processing time consumed by housekeeping tasks grows as processors apply increasing parallelism to accelerate number-crunching tasks. While most DSPs require the programmer or compiler to identify instructions that should execute in parallel, the ZSP500 uses a superscalar architecture that automatically identifies instructions that can execute in parallel. In some ways, this makes it easier to take advantage of parallelism on the ZSP500 than on most DSPs. However, superscalar processors have their own programming challenges. For example, to make full use of the processor’s available parallelism, the programmer or compiler must anticipate the processor’s instruction-scheduling decisions and arrange instructions accordingly. And while LSI Logic’s software and tools offerings are superior to those of most DSP core vendors, they still lag significantly behind those available for the best-supported DSP chips.
BDTI recently published a report that explores these and other
strengths and weaknesses of the ZSP500 in depth. For information on
this report, visit http://www.BDTI.com/products/reports_zsp500.html.
Excerpts from the report are available at
http://www.BDTI.com/articles/zsp500_summary_report.pdf.
Wireless MMX: A Look Under The HoodLast month Intel announced its “Wireless MMX” extensions for its ARM-based XScale architecture. Wireless MMX includes functionality equivalent to the integer components of the x86 MMX and SSE instruction sets. Like its x86 counterparts, Wireless MMX uses single-instruction multiple-data (SIMD) techniques to perform eight 8-bit, four 16-bit, two 32-bit, or (in a few cases) one 64-bit operation with a single instruction. Although the x86 and XScale implementations of MMX provide equivalent integer functionality, the underlying microarchitectures are dramatically different. For example, x86 processors use complex superscalar multiple-issue designs, while XScale uses a simple single-issue design. As a result, x86 MMX-optimized software will require substantial re-optimization for maximum performance on Wireless MMX-enabled XScale processors. However, Intel plans to support both MMX variants with its IPP library of DSP functions. (See the May 2002 DSP Insider at http://www.BDTI.com/dspinsider/archives/dspinsider_020501.html for details on IPP.) The data-type agility featured in Wireless MMX is common among PC-oriented processors, but is rare among embedded processors, particularly those that target battery-powered applications. The 8-bit capabilities of Wireless MMX are particularly notable, as they include operations that should greatly improve XScale’s performance in video and imaging applications. The 32-bit capabilities are also notable; they will make Wireless MMX an attractive target for audio applications. Despite its name, Wireless MMX does not include instructions specifically targeting wireless communications processing, such as instructions for accelerating Viterbi decoders. In addition to the new operations, Wireless MMX adds a bank of sixteen 64-bit registers. This register bank is unusually large. In comparison, the base XScale architecture contains sixteen 32-bit registers—and three of these registers are reserved for special uses. The large Wireless MMX register bank should reduce the need to shuffle data between registers and memory, which will increase application performance and reduce power consumption. In recent months, Intel and TI—among many others—have been posturing for dominance in so-called “application processors” for future mobile multimedia devices. With Wireless MMX, Intel hopes to bolster its position by increasing the ties between its PC-oriented processors and its application processors. The success of this approach will depend largely on how well the first Wireless MMX-enhanced processors perform in comparison to competitors like TI’s OMAP.
According to Intel, the first Wireless MMX-enhanced processors will be
available in eighteen months. Intel has not yet disclosed the
expected clock speeds or pricing for these processors.
BDTI Case Study
This Month: Designing a Processor for DSPAs digital signal processing finds its way into an ever-broader range of applications, processors that were not designed with signal-processing applications in mind are often called upon to perform substantial signal-processing tasks. At the same time, DSP processors are taking on new types of tasks—for example, processors designed for audio applications often must handle video as well. Often, the best way for a processor vendor to meet these expanding, evolving DSP requirements is to design a new processor. Designing a new processor involves difficult tradeoffs. For example, one way to meet new DSP application requirements is to abandon the current architecture and start over with a clean slate. This approach allows maximum flexibility in meeting application requirements, but it sacrifices compatibility. Other approaches involve modifying an existing architecture through techniques like extending the instruction set or adding a DSP coprocessor. These approaches can maintain compatibility, but may not provide an adequate increase in performance. Another complex design tradeoff involves balancing performance on a specific application against performance on a broad range of applications. Specialized features may have limited utility outside of a specific target application, but generic DSP features may provide insufficient performance for the target application. Designing application-specific features is especially tricky when the characteristics of the target application are in flux. In this situation, overly specialized features may become obsolete as target application requirements mature. Determining the best design for a processor requires knowledge of architectural options and application requirements, and an understanding of how architectural features map to application needs. With its extensive knowledge of existing architectures and hands-on experience in implementing signal processing applications, BDTI has a unique ability to help processor architects design processors for DSP applications. In one recent engagement, BDTI advised a major semiconductor manufacturer on expanding the capabilities of a general-purpose microprocessor family for signal processing-intensive applications. BDTI analyzed and characterized the demands of the target applications and weighed the available solutions, including instruction set extensions, use of a coprocessor, and design of an all-new architecture. BDTI recommended a strategy that provided practical solutions in the near term while also mapping out an attractive path for more powerful future processors.
To learn more about how BDTI can help you optimize your processor for
DSP applications, contact Jeremy Giddings (giddings@BDTI.com) or visit
http://www.bdti.com/products/services_advisory.html.
Impulse Response, by Jeff Bier
Time is MoneyExperienced engineers know that a comprehensive technical specification is a prerequisite for all but the most trivial projects. Without a solid spec, it is difficult to know how to begin a project, let alone deliver a high-quality product. Yet specifications are rarely complete in the sense that they rarely capture every minute element of the product’s ultimate behavior and performance. Indeed, attempting to specify every detail is usually futile: changing customer requirements, unforeseen implementation difficulties, and other troubles can beset even the best specifications. Wise engineers create balanced specs that lay out a clear framework without wasting time on trivial details. Just as a specification is needed to define the technical framework for a product, a contract is needed to define the framework for a business transaction. For example, outsourcing development tasks without a good contract can create product-killing disputes over intellectual property ownership. But overly ambitious contracts are just as inefficient as over-reaching technical specs. Too often, unnecessarily complex and lengthy contracts delay product development and increase costs while providing no benefit to the involved parties. Unfortunately, many companies seem to think that the length of a contract is proportional to its quality. In fact, the opposite is often true, particularly when contracts are bloated with “standard terms” that have little bearing on the project at hand. A blind insistence that the supplier accept the customer’s standard terms—common among electronics industry behemoths—is particularly regrettable during the current downturn. The resources spent analyzing and negotiating 10,000-word contracts would be much better spent on research and development. And in competitive markets where time-to-market is king, wasting even a few weeks haggling over inappropriate contract wording too often leads to a compressed development schedule, over-worked engineers, and missed opportunities.
Engineers understand that while some generic elements of a technical
specification can be applied to many products—and should be for the
sake of efficiency—it is ridiculous to blindly apply the same spec to
projects with fundamentally different goals. Perhaps if the engineers
and the lawyers had lunch together now and then, companies would adopt
a similarly thoughtful approach for their contracts.
Join BDTI in Supporting GSPx/ISPCA new trade show and conference organized by Amnon Aliphas, the founder of ICSPAT/DSP World, the Global Signal Processing Expo (GSPx) and International Signal Processing Conference (ISPC) is specifically aimed at filling the market’s need for a peer-to-peer horizontal DSP show for engineers. The event will be held at the Hotel Intercontinental in Dallas, Texas, from March 31 to April 3, 2003. The technical conference will combine workshops and conference presentations with panel sessions led by industry leaders on compelling topics that impact the direction of DSP technology. The industry expo will provide a venue for companies to introduce and demonstrate new technologies and products.
More information on GSPx and ISPC is available on the GSPx Web site at
http://www.gspx.com/ISPC/index.html.
Microprocessor Forum 2002, October 14-17, in San JoseThe fifteenth annual Microprocessor Forum (MPF) will be held from October 14 to 17 at the Fairmont Hotel in downtown San Jose. MPF is a key semiconductor industry event where new microprocessors and related technology are announced. It draws processor architects, technical managers, system designers, financial analysts, and the technical and general press. BDTI will be at the MPF Expo Night, to be held from 5:45 to 8:45 PM on Tuesday, October 15, in the Regency Ballroom. Stop by to browse BDTI’s latest reports and talk to BDTI analysts.
For details about MPF, go to http://www.mdronline.com/mpf.
Groundbreaking FPGAs for DSP Report Now ShippingFPGAs for DSP provides a detailed assessment of the DSP capabilities of DSP-capable FPGAs and why FPGAs are a compelling solution for some DSP applications. The report discusses new offerings from Altera and Xilinx and includes benchmark results of FPGA DSP performance.
Details of the report, including excerpts from BDTI’s analysis and a
table of contents, may be found on BDTI’s Web site at
http://www.BDTI.com/products/reports_focus.html.
New Inside Report Analyzes the LSI Logic ZSP500BDTI announces a new Inside report on the LSI Logic ZSP500, itself newly announced. The ZSP500 is a superscalar DSP core available for license from LSI Logic that targets cost- and power-sensitive applications. Like the ZSP400, the ZSP500 features two 16-bit MAC units. However, the ZSP500 is considerably faster than the ZSP400—and is faster than many other dual-MAC DSP architectures. This report provides a comprehensive qualitative analysis of the processor’s architecture and features, along with a complete quantitative performance analysis based on the BDTI Benchmarks™ . The DSP performance of the ZSP500 is compared to that of key competitors, with benchmark results analyzed in terms of underlying architectural strengths and weaknesses.
For details on Inside the LSI Logic ZSP500, including excerpts from
BDTI’s analysis and sample benchmark results, go to
http://www.BDTI.com/products/reports_zsp500.html. Excerpts from the
report are available at
http://www.BDTI.com/articles/zsp500_summary_report.pdf.
About BDTIBDTI is an independent source for DSP technology analysis and optimized DSP software. From rigorous technical analyses of processors for DSP, such as the Inside series of processor analyses, to highly regarded technology training classes, BDTI is the trusted independent source for reliable information on DSP technology.
For more information, visit our Web site at http://www.BDTI.com.
The next issue of BDTI’s DSP Insider is coming in November. Previous issues of BDTI’s DSP Insider are archived on BDTI’s Web site. Follow the link from http://www.BDTI.com/dspinsider.htm. If you have comments, suggestions, or other feedback about the DSP Insider please send email to dspinsider@BDTI.com. BDTI’s DSP Insider is a free monthly electronic newsletter published by Berkeley Design Technology, Inc. If our newsletter was forwarded to you and you would like to receive it regularly, please register at http://www.BDTI.com/dspinsider.htm.
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