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Vol. I, No. 6 BDTI's DSP Insider October 2001
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This month:
*** New DSP Architectures to Debut at MPF
*** Intrinsity Aims for Super-fast Embedded Processors
*** Evaluating Compilers for DSP Applications
*** "Impulse Response," a news analysis and opinion column written
by Jeff Bier, BDTI's General Manager, and featured in EE Times
*** BDTI offers "Processors for DSP" Seminar at MPF 2001
*** BDTI goes "Inside" Hitachi, StarCore, Hitachi/STMicro, 3DSP,
and ARM Processors
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*** New DSP Architectures to Debut at MPF
Despite the current industry slowdown, many companies are continuing
to produce new architectures for DSP applications. At the upcoming
Microprocessor Forum, two startups and one established player—
Siroyan, 3DSP, and LSI Logic, respectively—will disclose next
generation high performance licensable DSP core architectures.
Siroyan will unveil the SRA328—an architecture that uses VLIW
techniques and integrates DSP, RISC, and MMU technology. The SRA328
can have up to 32 separate execution units—an impressive level of
parallelism. 3DSP will reveal its SP-20 "UniPHY" processor core.
This superscalar architecture targets broadband applications using a
SIMD approach and RISC-like features. LSI Logic will disclose the
ZSP600, its second-generation superscalar DSP core based on the ZSP
architecture.
Another very interesting architecture that will be disclosed at MPF is
Broadcom's "Spice Engine" vector signal processor, which targets
networking and communications applications.
Microprocessor Forum will take place October 15-19 in San Jose.
Further information is available at www.mdronline.com/mpf/index.html.
*** Intrinsity Aims for Super-fast Embedded Processors
Intrinsity, a startup in Austin, Texas, recently disclosed its new
Fast14 technology—a collection of design techniques that enable
high-speed dynamic logic to be implemented on standard CMOS processes.
This technology will facilitate clock speeds of up to 2.2 GHz.
Intrinsity plans to apply this new technology to developing its own
high-end embedded processors, which most likely will target the wired
and wireless communications infrastructure markets.
Fast14 Technology achieves its speed increases in four ways. First,
it uses a four-phase uniform overlapping clocking scheme that
eliminates the need for latches. This unique clocking approach
addresses the problem of race conditions typically associated with
dynamic logic. Second, "1-of-N Dynamic Logic" (NDL) reduces the
number of gate delays required to implement a logic function. Third,
"Wire Twizzling"—a patented method for routing NDL signals—reduces
coupling noise and improves signal speed with no area penalty,
according to Intrinsity. Finally, an EDA tools suite automates the
creation of dynamic logic circuits.
Intrinsity has already achieved speeds of 2.2 GHz on a 0.18-micron
CMOS process with aluminum interconnections, but this was only a test
chip with limited functionality. Moreover, chips produced with Fast14
technology have thus far consumed power commensurate with their
increased speeds. Lower power consumption will likely be a crucial
factor in Fast14's success, as even line-powered communications
infrastructure applications are sensitive to power consumption due to
heat-dissipation concerns.
*** BDTI Case Study
This month: Evaluating Compilers for DSP Applications
In the modern DSP world, the evaluation of compilers is becoming
increasingly important. There are several reasons for this. First,
as applications require larger and more complex software, it is
becoming impractical to code applications entirely in assembly
language, as was once common. Second, processors are getting more and
more complex—a point exemplified by TI's 'C6000 series. This
increased complexity yields increased difficulty in optimizing
assembly code for such processors. Finally, given the rate at which
processors are changing, users are less willing to be locked into a
specific architecture; developing software using high-level languages
facilitates migration between processors.
However, there is a serious problem in shifting from assembly to
high-level languages. C compilers often generate inefficient code for
DSP applications. Compiler users must either accept this inefficient
code or replace significant portions of compiler-generated code with
hand-crafted assembly code. This hand optimization—the very thing
that compilers provide an alternative to—is often required in order
to realize the full potential of a processor, and today's competitive
DSP applications require all of a processor's available resources.
Processor users are therefore motivated to understand the relative
capabilities and efficiency of compilers for DSP applications.
In response to the increasingly important role played by compilers,
BDTI began an internal effort several years ago to evaluate C
compilers. This investigation revealed a great deal of variation
among compilers; for example, among the evaluated compilers, the ratio
of compiled code size to hand-optimized assembly code size varied by
as much as a factor of ten. BDTI is now preparing to begin the
roll-out of its C compiler evaluation offerings. Interested parties,
processor vendors, and compiler vendors should contact Jeremy Giddings
at BDTI (giddings@bdti.com) for further information.
*** Impulse Response, by Jeff Bier
This month: Talkin' Trash
It used to be that DSP was a niche technology because only
cost-insensitive applications could afford the hardware required for
serious real-time signal processing. Over time, however, the prices
of DSP-capable processors and ASICs have dropped to the point that DSP
is now used in many consumer products, cell phones most prominent
among these. But have we begun to get carried away?
Two companies, Hop-On Wireless and Dieceland Technologies, plan to
release disposable cell phones next month. These small, cheap devices
are made by incorporating cell phone circuitry onto a paper substrate.
They will come with prepaid calling time for outgoing calls only; when
the minutes are up, these phones are ready for the garbage.
Despite popular monikers describing these products—"talk-and-trash,"
"chat-and-chuck"—manufacturers are touting their recyclability.
These sentiments ring hollow, however, when the products' key feature
is disposability.
While it is gratifying to see that DSP chips are inexpensive enough to
be used in disposable products, it is nonetheless disturbing to see
that they actually are being used in disposable products. Do we
really want millions of batteries and cell phone ASICs clogging our
landfills?
Environmental considerations aside, disposable cell phones seem like a
solution looking for a problem. Perhaps the most compelling
application I've heard of for these phones is promotional giveaways.
But even this is silly—flimsy, disposable products hardly convey the
image that most companies would like to project. And a giveaway that
is tossed in the trash a few hours after it is received won't exactly
serve as a lasting reminder of the company whose logo it bears. I'll
take a good t-shirt any day—I can always use it to dust my shelves,
and I won't have to worry about it dissolving if I get caught in the
rain.
Disposable cell phones won't be as cheap as we might expect; they'll
cost up to $30 with an hour of airtime. Despite this, though, reports
are that manufacturers have orders for a hundred million disposable
phones.
This is technology run amok. Just because something is possible
doesn't make it a good idea. Instead of using our best technology to
find ways of consuming resources ever more quickly, perhaps we should
use it to help us tread less heavily on the planet.
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*** BDTI offers "Processors for DSP" Seminar at MPF 2001
The only public presentation of BDTI's highly rated seminar,
"Processors for DSP: Architectures and Trends," will be this year on
Friday, October 19 at the Fairmont Hotel in San Jose in conjunction
with the Microprocessor Forum. There's still time to register. Newly
updated to include current high-profile devices as well as
soon-to-be-announced architectures, this seminar will help both
experienced professionals and new entrants to the processor world
understand the choices available in the crowded marketplace of
processors targeting DSP applications. The performance, strengths,
and weaknesses of key architectures will be covered. MPF 2001 will be
held at the Fairmont Hotel in San Jose from October 15 to 19.
"Processors for DSP" will be offered on Friday, October 19.
For more information on this and other industry events, go to
www.BDTI.com/bdti_whatsnew.htm.
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*** New "Inside" Reports
BDTI continues to roll out detailed analyses of key processors
targeting digital signal processing applications. BDTI's "Inside"
series of technical reports combine benchmarking, in-depth evaluation
of architecture, performance, and features, and expert analysis based
on BDTI's extensive knowledge and experience.
Now shipping:
"Inside the StarCore SC110" explores the low-power VLIW single-MAC DSP
core jointly developed by Agere and Motorola.
"Inside the Hitachi SH-DSP and SH3-DSP" covers two hybrid
DSP/microcontroller architectures in Hitachi's SuperH family, among
the most successful DSP-enhanced microcontrollers.
Scheduled for publication this fall:
"Inside the 3DSP SP5" provides the first detailed study of 3DSP's
fixed-point SP5 processor core with SuperSIMD(tm), combining a
superscalar architecture with SIMD.
"Inside the ARM ARM7, ARM9, and ARM9E" provides a comparison of the
DSP capabilities of three ARM cores, the widely-used ARM7, the newer
ARM9, and the ARM9's enhanced sibling, the ARM9E.
"Inside the Hitachi SH-4/STMicroelectronics ST40 and Hitachi
SH-5/STMicroelectronics ST50" provides detailed analysis of the two
processor cores jointly developed—but differently named—by Hitachi
Semiconductor and STMicroelectronics.
Watch for publication dates, excerpts from BDTI's analysis, and
example benchmark results on BDTI's Web site at www.BDTI.com.
For information on all of BDTI's technical reports, go to
www.BDTI.com/products/services_overview.htm#publications.
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*** BDTI Is Hiring
Despite these tough economic times, BDTI's business continues to grow,
and we are looking for a few high caliber professionals to join our
team. Both entry level and senior positions are available for DSP
Analysts and Embedded Software Engineers. For more information,
please see www.BDTI.com/jobs_employment.htm.
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*** About BDTI
BDTI is an independent source for DSP technology analysis and
optimized DSP software. From rigorous technical analyses of
processors for DSP, such as the "Buyer's Guide to DSP Processors," to
highly regarded technology training classes, BDTI is the trusted
independent source for reliable information on DSP technology. For
more information, visit our Web site at www.BDTI.com.
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The next issue of BDTI's DSP Insider is coming in November. An archive
of previous issues of the BDTI DSP Insider will be up soon on BDTI's
Web site. If you have comments, suggestions, or other feedback about
the DSP Insider, please send email to dspinsider@bdti.com.
BDTI's DSP Insider is a free monthly electronic newsletter published
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BDTI's DSP Insider (c) 2001 Berkeley Design Technology, Inc.
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