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Vol. I, No. 3 BDTI's DSP Insider July 2001
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This month:
*** ADI announces Micro Signal Architecture device
*** News from EPF: Heterogeneous DSP Designs
*** Floating-Point to Fixed-Point Conversion
*** "Impulse Response," a news analysis and opinion column written
by Jeff Bier, BDTI's General Manager, and featured in EE Times
*** BDTI analysis of the ADI/Intel Micro Signal Architecture
*** BDTI Benchmarks(TM)
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*** ADI's New Micro Signal Architecture-based Device
Analog Devices (ADI) announced this month the first device based on
the Micro Signal Architecture (MSA), a new 16-bit fixed-point DSP
architecture jointly developed by ADI and Intel. The ADSP-21535, the
first in ADI's new "Blackfin" family, joins an already competitive
field of low-power, moderate-performance architectures that target
portable communications applications. Several attributes of the MSA,
however, might well distinguish it from the rest of this pack, which
includes the TI 'C55xx, the STMicroelectronics ST100, and StarCore
SC100-based devices.
MSA features that differentiate it from the competition include power
management capabilities that allow a single device to operate at a
wide variety of voltages and clock speeds, and extensive support for
8-bit ALU operations (to accelerate video algorithms). The MSA also
maintains the orthogonality of a VLIW instruction set architecture
without sacrificing ease of assembly language programming. BDTI's
benchmark analysis of the MSA suggests that, if the ADSP-21535
achieves its projected 300 MHz clock speed, it will be approximately
twice as fast as the 160 MHz TI 'C55xx and about half as fast as
Motorola's 300 MHz SC140-based MSC8101. The energy consumption of the
ADSP-21535 varies according to its operating voltage and clock speed.
At 300 MHz and 1.5 V, the ADSP-21535 has a projected energy
consumption that is about 40% higher than that of the 'C5510 and
roughly three times higher than that of the MSC8101. At 100 MHz and
0.9 V, the ADSP-21535 has a projected energy consumption that is about
40% lower than that of the 'C5510 and only 25% higher than that of the
MSC8101.
The ADSP-21535 is scheduled to begin sampling in September 2001. An
in-depth analysis of the MSA is available in BDTI's new report,
"Inside the ADI/Intel Micro Signal Architecture."
*** News from EPF: Heterogeneous DSP Designs
Three new DSP architectures were presented at the Embedded Processor
Forum in San Jose last month. All three architectures are
heterogeneous, i.e., they each combine a DSP with other performance
enhancing hardware. All three architectures also target
communications applications.
It is already common in communications applications to find boards
that combine DSPs, general-purpose processors, reconfigurable logic,
and ASICs, albeit with each on a separate chip. As the potential for
integration increases and these different elements can be included on
the same die, there will be a great demand to capitalize on the
benefits of doing so-reduced cost, size, and power consumption
foremost among these. The three architectures presented at EPF
suggest that this trend is already underway.
The first device presented at EPF was the Texas Instruments
TMS320C6416. This chip was announced earlier this year and combines
TI's 'C64xx DSP core with two coprocessors. A full analysis of the
'C64xx core is available in Buyer's Guide to DSP Processors, 2001
edition.
The second architecture was BAZIL, which was jointly developed by LSI
Logic and Ericsson. BAZIL targets communications infrastructure
equipment by integrating LSI's "ZSP" DSP core with two ePLCs
(reconfigurable logic blocks). Subtasks of an application are mapped
onto either the ZSP core or an ePLC according to the complexity and
computational demands of the sub-task. The ePLC can handle the more
computationally demanding functions that are less complex and more
repetitive while the ZSP core takes care of the more complex but less
computationally demanding functions.
LSI licensed the ePLC technology from Adaptive Silicon, and this
acquisition has neatly rounded out LSI's IP portfolio for
communications applications—it now offers reconfigurable logic, DSP
cores, general-purpose processor cores, and ASIC capability. This
puts LSI in a strong position: it can offer ASIC customers a diverse
array of building blocks; moreover, LSI can draw from these elements
in its own ASSP designs. If nothing else, BAZIL is good proof of
concept for LSI's integration capabilities.
But how effective is this combination? LSI presented FFT benchmark
data, but the data suggests that on this benchmark the ZSP and two
ePLCs would not be as fast as, e.g., Motorola's SC140-based MSC8102.
Speed, however, was probably not LSI's only consideration; there was,
after all, a development partner, and Ericsson likely achieved its
application-specific goals with BAZIL.
The third DSP architecture shown at EPF was the new SkyCore from
STMicroelectronics. This heterogeneous design combines an ST120 DSP
and an ARM7 general-purpose processor and targets automotive media
applications, e.g., receiving digital broadcasts in a car. The
SkyCore is a highly integrated SoC with many specialized I/O
interfaces and on-chip peripherals.
An interesting question about the SkyCore is why it uses an ARM7 when
the ST120 is marketed as having strong general-purpose processing
capabilities in addition to its DSP features. Perhaps the ARM7 was
used in an effort to optimize energy consumption: the ST120 is a
fairly heavyweight processor that requires fast memory, while the ARM7
can get by with much slower memory. When low power consumption is
required the DSP could simply be shut down, with the ARM7 performing
interface and supervisory tasks.
As communications products continue to demand increased processor
power while simultaneously demanding reduced cost, size, and energy
consumption, heterogeneous designs like these will cease to have
novelty status. Rather, they will become the mainstream solution.
*** BDTI Case Study
This month: Floating-Point to Fixed-Point Conversion
Many signal-processing algorithms are initially developed using
floating-point data types on desktop platforms. However, many DSP
algorithms are ultimately implemented in products that employ
fixed-point processors. This is particularly true for portable
consumer products like PDAs and cell phones. For demanding DSP
algorithms, emulating floating-point arithmetic on fixed-point
processors can be prohibitively slow. Hence, converting algorithms
from floating-point to fixed-point is essential. But such conversion
must be done carefully to avoid compromising output quality.
To assist in floating-point to fixed-point conversion, BDTI has
developed a proprietary tool suite that collects data on the numeric
behavior of a floating-point algorithm and then efficiently emulates
arbitrary-precision fixed-point operations within the algorithm. BDTI
recently applied this tool suite to an audio decoder implementation
that required a quick conversion from floating-point to fixed-point,
but also required that the level of output quality be preserved. As
more multimedia applications migrate from PCs to embedded devices, the
need for efficient fixed-point implementations of functions like audio
decompression is increasing.
BDTI's software services business focuses on developing optimized
implementations of streaming media functions for a wide range of
processors. For details see http://www.BDTI.com.
*** Impulse Response, by Jeff Bier
This month: "Hetero-genius Designs for DSP"
Business guru Michael Porter once observed that the U.S. railroads
failed because they took too narrow a view of their business. They
thought their business was just the railroads—in fact it was
transportation.
DSP processor vendors are now at the crossroads of what could be a
similar situation. If they take the narrow view that their business is
just DSPs, they might go the way of the U.S. rail system. On the other
hand, if they see themselves as DSP applications solution providers—
where DSPs are only part of a heterogeneous solution—they will
continue to thrive.
The reason for this is simple: application demands are growing faster
than processor performance levels. For example, while 2G cellular
systems are well served by DSP processor capabilities, 3G solutions
are far beyond the reach of DSP processors alone. Vendors serious
about targeting these advanced applications are forced to use
heterogeneous designs that combine a DSP with other types of hardware.
Heterogeneous design has many benefits. Even within a typical
DSP-intensive communication product there are many different kinds of
algorithms whose computational demands vary radically. Data rates,
even within the same system, can vary by many orders of
magnitude. Data types are similarly diverse. Expecting one type of
architecture—whether a DSP processor or something else—to address
these wildly divergent requirements with a high degree of efficiency
is both naive and futile.
With heterogeneous solutions, designers capitalize on the fact that
different kinds of implementation technology are good at different
things. And many different things go on inside today's DSP
applications, even within such outwardly simple products as cell
phones. As more and more DSP-based applications converge in consumer
products—e.g., a cellphone/PDA/MP3 player—the diversity of
requirements within these products increases.
The future belongs not to the vendor with the fastest DSP, but to the
vendors who skillfully combine multiple implementation technologies in
heterogeneous designs tailored to the needs of key applications.
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*** BDTI Analysis of the ADI/Intel MSA now available
BDTI is now shipping "Inside the ADI/Intel Micro Signal Architecture,"
the latest in the "Inside" series of in-depth individual processor
analyses. This report includes benchmarks and in-depth analysis of the
low-power dual-MAC DSP core jointly developed by Analog Devices and
Intel.
For details see http://www.BDTI.com/products/reports_msa.htm.
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*** BDTI Benchmarks(TM) available for licensing
The BDTI Benchmarks(TM), BDTI's proprietary methodology for processor
benchmarking, are available for licensing. A suite of twelve
algorithm kernels that represent key DSP operations, the BDTI
Benchmarks provide processor developers with an independent means of
evaluating architectures.
Contact BDTI at info@BDTI.com for details.
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*** About BDTI
BDTI is an independent source for DSP technology analysis and
optimized DSP software. From rigorous technical analyses of
processors for DSP, such as the "Buyer's Guide to DSP Processors," to
highly regarded technology training classes, BDTI is the
industry-independent source for reliable information on DSP
technology. For more information, visit our Web site at www.BDTI.com.
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The next issue of BDTI's DSP Insider is coming in August.
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BDTI's DSP Insider (c) 2001 Berkeley Design Technology, Inc.
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