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Vol. I, No. 1 BDTI's DSP Insider May 2001
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This month:
*** Texas Instruments Announces the First 'C64xx Family Members
*** Conexant Licenses LSI Logic's ZSP Core for Wireless Mobile
Applications
*** "Impulse Response," a news analysis and opinion column written
by Jeff Bier, BDTI's General Manager, and featured in EE Times
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*** Texas Instruments Announces the First 'C64xx Family Members
Texas Instruments recently announced its first three products based on
the 'C64xx DSP core: the TMS320C6414, TMS320C6415, and TMS320C6416.
All three devices are scheduled to begin sampling in June 2001, about
a year and a half after TI originally announced the core. The target
speed for initial samples remains an aggressive 600 MHz, but 400 and
500 MHz versions of each device will also be available.
Prices for the 400 MHz 'C6414 begin at $95, with prices for the 'C6415
and 'C6416 scaling higher by 10% each. The price of 400 MHz chips is
comparable to another ultra high-performance DSP, Motorola's $96
SC140-based 300 MHz MSC8101, which provides similar performance. At
speeds greater than 400 MHz, however, the 'C64xx chips begin to gain
an edge on the '8101, and users of 'C62xx chips have
'C64xx-compatability as a powerful incentive to stay with the 'C6xxx
family. Lucent's StarPro2000, containing three 300 MHz SC140 cores
and scheduled for production later this year, will ensure that the
competitive landscape for 'C64xx chips remains heated.
The 'C6414 targets general-purpose DSP applications with peripherals
that include an enhanced 64-channel DMA controller, two external
memory interfaces (16-bit and 64-bit), three multi-channel buffered
serial ports, and a 32-bit host port interface. The 'C6415 is focused
on media applications, supplementing the 'C6414 with a PCI bus and an
optional Utopia 2 ATM interface. The 'C6416 tackles 3G wireless
infrastructure applications, adding a Turbo coprocessor with
programmable parameters and a Viterbi coprocessor to the complement of
peripherals on the 'C6415.
Like some of their 'C62xx predecessors, the first three 'C64xx chips
will feature a two-level cache made up of two 16K level-one (L1)
caches (one for data and one for memory) and a single, unified 1M
level-two (L2) cache. The size of the L2 cache is more than seven
times larger than TI initially announced, and several other features
have also been enhanced; e.g., the 64-channel DMA controller has twice
as many channels as TI originally planned. Speed, however, is not
among these enhancements: 1.1 GHz chips—which accounted for much of
the hype surrounding the announcement of 'C64xx products—are not
expected until sometime in 2002.
*** Conexant Licenses LSI Logic's ZSP Core for Wireless Mobile
Applications
On March 16 LSI Logic announced that it will license its ZSP core to
Conexant for use in wireless mobile applications. Following on the
heels of Broadcom and IBM, Conexant's deal with LSI Logic is a strong
endorsement of the ZSP's potential as a licensable core—a potential
that has not always been clear.
In 1998 ZSP Corporation, the original developers of the core,
demonstrated silicon at a then-impressive 200 MHz, but the
architecture was unable to get traction in the market. BDTI analyzed
the architecture and found that it had strong DSP performance (for
that time) and exceptionally good code density. But there weren't any
takers. LSI later acquired the technology, but its initial silence
about how it planned to use the ZSP core left us wondering whether the
architecture had a real future. However, with Broadcom, IBM, and now
Conexant backing the core, it appears that the ZSP core is finally
gaining market momentum.
Not entirely clear is Conexant's rationale for using the superscalar
ZSP in wireless mobile applications: superscalar processors tend to be
relatively power-hungry, which is one reason why they are not commonly
used in DSP processors, and thus far are nearly unheard of in
power-sensitive DSP applications. Indeed, ZSP Corporation itself had
originally promoted the architecture for communications
infrastructure, not for mobile applications.
Also interesting is that Conexant is licensing a DSP core at all; the
company has historically used its own home-grown DSP architectures.
In response to difficult market conditions and falling stock prices,
Conexant might be trying to cut costs by sharing development expenses.
Or perhaps they, along with IBM and Broadcom, have found a compelling
reason to begin using the ZSP core almost two years after its
acquisition by LSI Logic.
*** Impulse Response, by Jeff Bier
This month: "Caveat Emptor"
In the ancient Near East the number 40 was a literary device
symbolizing "an impressively large number," not a precise quantity.
"It rained for 40 days and 40 nights," "they wandered in the desert
for 40 years,"—the examples are countless.
In the modern world of DSP processors, the term "10X" has taken on a
similar function. Vendor claims that a processor is, e.g., "10X
faster than existing DSPs," often don't mean that the processor is
really 10 times faster—only that it is "much faster." The problem, I
suppose, is that "much faster" just doesn't resonate as strikingly in
a press release.
While overblown marketing claims are nothing new, the rapid expansion
of the DSP market in recent years has created an increasingly
competitive sales environment. This has made processor vendors—even
some of the very largest—desperate to get our attention. Many have
resorted to hyperbole, which can obscure a new processor's true
capabilities.
In the old days (say, five years ago), DSPs generally had very similar
architectures. This made comparing processors fairly simple: the main
performance differentiator was clock speed, and simple performance
metrics like MIPS provided useful information.
The increasing diversity of both DSP architectures and applications
has now rendered clock speed and simple performance metrics useless in
assessing processor performance, and has complicated processor
comparisons. We frequently see cases where processor A is twice as
fast as processor B on, e.g., an FFT, but twice as slow on another DSP
algorithm, e.g., a Viterbi decoder.
This highlights the importance of using appropriate benchmarks to
compare processors for DSP applications: not just any benchmarks, but
benchmarks that are representative of the target application.
Unfortunately, hyperbolic performance claims ultimately hurt everyone
involved. System designers who naively accept exaggerated claims may
find—often too late—that their systems don't meet their design goals.
Reporters and market analysts who parrot these claims lose credibility
with their readers. Processor vendors making such claims lose the
trust of their customers, if not their business.
These days, getting educated is the only way to avoid getting burned:
processor performance claims should be evaluated with both caution and
a healthy dose of skepticism.
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*** About BDTI
BDTI is an independent source for DSP technology analysis and
optimized DSP software. From rigorous technical analyses of
processors for DSP, such as the "Buyer's Guide to DSP Processors," to
highly regarded technology training classes, BDTI is the
industry-independent source for reliable information on DSP
technology. For more information, visit our Web site at www.BDTI.com.
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*** Upcoming Events
Look for BDTI at ConVergence University, May 30 to June 1. BDTI will
offer two tutorials: "Processor Options for DSP Applications:
Microprocessors versus DSPs" and "Selecting Processors for DSP
Applications." "Processor Options for DSP Applications" will focus on
helping engineers determine processor requirements for DSP
applications and whether a microprocessor or DSP is the best choice
for their application. "Selecting Processors for DSP Applications"
will discuss the key questions that should be addressed when selecting
a processor for DSP, including use of processor benchmark results and
application profiles in a sample processor selection exercise. To
register, go to www.convergenceu.com/usa.
At this year's Embedded Processor Forum, BDTI will present two of its
highly rated seminars, both revised and updated for 2001. On Monday,
June 11, BDTI will present "DSPs and Alternatives for Communications
Applications." On Friday, June 15, plan to attend "Digital and
Streaming Audio: Applications, Algorithms, and Processors." On
Wednesday, June 13, Jeff Bier—General Manager of BDTI—will lead a
conference session entitled "Communications Processors: the DSP
Route." Look for BDTI at the Embedded Processor Expo on Tuesday and
Wednesday nights. Stop by our table for a chat, to pick up a new
Pocket Guide to DSP Processors and Cores, or to find other useful
information. To register, go to www.mdronline.com/epf.
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The next issue of BDTI's DSP Insider is coming in June. In addition
to Jeff Bier's "Impulse Response," look for articles on new products
from NEC and ADI—what do these new offerings say about these
companies' directions?
BDTI's DSP Insider is a free monthly electronic newsletter published
by Berkeley Design Technology, Inc. If our newsletter was forwarded
to you and you would like to receive it regularly, please register at
www.BDTI.com/dspinsider.htm.
If you no longer wish to receive the DSP Insider, send an email message
to dspinsider@bdti.com with the words, "Remove me," in the subject line.
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BDTI's DSP Insider (c) 2001 Berkeley Design Technology, Inc.
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