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BDTI Benchmarks™ results for the ARM Cortex-A8
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ARM Cortex-A8 Benchmark Results

About the ARM Cortex-A8

The Cortex-A8, announced in 2005, is a 32-bit licensable core developed by ARM Limited. It implements the ARMv7 instruction set. One major difference between the Cortex-A8 and previous ARM cores is the addition of the NEON instruction set extensions designed to accelerate multimedia tasks. Using these extensions, the Cortex-A8 can execute up to four 16-bit multiply-accumulate instructions per cycle (versus two for the ARM11). The Cortex-A8 targets chips in high-performance cellular handsets, as well as set-top boxes, printers, and automotive infotainment applications.


The Cortex-A8 uses a superscalar (first for an ARM core), dual-issue, in-order execution pipeline. The pipeline, unusually long, comprises a 13-stage main pipeline and a 10-stage NEON pipeline for data-processing execution. In contrast, ARM11's pipeline has only 8 stages. According to ARM, the Cortex-A8's long pipeline will enable high clock rates—potentially exceeding 1 GHz in a 65 nm process.


Unlike ARM’s other licensable cores, the Cortex-A8 is intended to be implemented using either a typical logic synthesis methodology (as is almost always done with ARM's other licensable cores) or a highly optimized semi-custom design style. Initial Cortex-A8 licensees creating highly optimized implementations of the Cortex-A8 may apply hand-crafted library cells and other physical-level optimizations for improvements in both frequency and power over traditional synthesis methodologies. As a result, BDTI does not have clock speed, silicon area, and power consumption data for the Cortex-A8 based on BDTI's standardized conditions for processor cores. Caution should therefore be used when comparing BDTI's Cortex-A8 benchmark results with results for other processor cores.



BDTI DSP Kernel Benchmarks™ Cortex-A8 Results

BDTI DSP Kernel Benchmarks™ results for the Cortex-A8 specify BDTIsimMark2000™ per MHz. Multiply this figure by projected clock rate to obtain projected BDTIsimMark2000™.

                             
                             
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Processor Family

Clock Rate
(MHz)

BDTISimMark2000™

ARM Cortex-A8
N/A
7.6 per MHz
For more detailed Cortex-A8 benchmark results, see BDTI’s offerings of results for ARM processors or contact BDTI.

Table 1.  ARM Cortex-A8 Performance on BDTI DSP Kernel Benchmarks™


Processor Family

Clock Rate
(MHz)

BDTImemMark2000™

ARM Cortex-A8
N/A
78

Table 2.  ARM Cortex-A8 Memory Efficiency on BDTI DSP Kernel Benchmarks™


BDTI Video Encoder and Decoder Benchmarks™ Cortex-A8 Results

BDTI Video Encoder and Decoder Benchmarks™ results for the ARM Cortex-A8 are reported at the following two operating points:

  • QVGA Operating Point. At this operating point the benchmarks process a video sequence at QVGA resolution (320x240) with a frame rate of 30 fps. This is appropriate for mobile applications such as cell phones that have small displays.
  • D1 Operating Point. At this operating point the benchmarks process a video sequence at standard-definition television resolution (720x480, also known as “D1” resolution) with a frame rate of 30 fps. This is appropriate for applications such as personal media players (PMPs), digital surveillance equipment, and set-top boxes.

BDTI Video Encoder and Decoder Benchmarks™ results for the Cortex-A8 specify cycles/s. Divide this figure by projected clock rate to obtain projected processor utilization.


BDTI Video Decoder Benchmark™


QVGA (320x240)

                               

d

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D1 (720x480)

                             

d

certifiedlogo certifiedlogo VEDB Certified


BDTI Video Encoder Benchmark™

QVGA (320x240)

                               

d

certifiedlogo certifiedlogo VEDB Certified




QVGA
Decode

D1
Decode

QVGA
Encode

Cycles / s
(millions)

Cycles / s
(millions)

Cycles / s
(millions)

ARM  Cortex-A8 114
504
421

Table 1.  ARM Cortex-A8 Performance on BDTI Video Encoder and Decoder Benchmarks™ for Specified Operating Points



Clock Speed


(MHz)

L1
 Instruction
Cache


(Kbytes)

L1
Data
Cache


(Kbytes)

L2
 Cache


(Kbytes)

On-chip
Main
Memory


(Mbytes)

External
Memory
 Speed


(MHz)

External
Memory
Bus width

(bits)

ARM  Cortex-A8 
N/A
16
16
128
N/A
1/3 CPU Clock Rate
64

Table 2.  Processor Architectural Details

For a complete list of BDTI benchmark suites and additional results, visit http://www.bdti.com/bdtimark/benchmarks.htm.

No reproduction or reuse is permitted without the express authorization of BDTI.

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