General-purpose processors are inefficient at executing the mathematical operations common in digital signal processing (DSP), and their inefficiency gave rise to processors specialized for DSP. Whereas signal processing makes heavy use of sums of products—multiply-accumulates (MACs), in DSP parlance—general-purpose processors typically required many cycles to compute a single multiplication.
Early DSP processors used specialized multiplication hardware and instructions to achieve fast multiplications, and contained additional hardware, such as wide accumulator registers, to increase numeric fidelity. Such early DSPs as the TMS32010 (circa 1982) from Texas Instruments Inc., Dallas, operated at about 5 MHz. Execution of a single MAC on a TMS32010 required two instruction cycles, or 400 ns. Clock speeds of current mainstream DSPs have increased to between 50 and 100 MHz, with the newest processors executing at 200 MHz or higher.
Performance has increased even more than the relative clock speeds would suggest, however, as current architectures can pack much more work into an instruction cycle than earlier devices. For instance, some high-end DSP processors include two multiplication units, and can compute two MACs in every instruction cycle. At 200 MHz, each MAC pair thus requires only 5 ns.
In addition to fast MAC computation, DSP processors provide a variety of hardware support and instruction-set support for operations that are common in DSP. These include hardware support for zero-overhead looping, separate address-generation units specialized for DSP, and support for bit manipulation.
As to the first of these, most DSP algorithms spend much of their processing time in loops. So most DSP processors include hardware that lets the programmer implement a loop without squandering cycles on decrementing the loop counter, comparing its value against the target value, and branching to the top of the loop.
The highly specialized addressing modes used in DSP include "bit-reversed" addressing, which is useful for unscrambling the output of the fast Fourier transform—a commonly used DSP algorithm that transforms a time-domain signal into its frequency-domain representation. Implementing bit-reversal in software is much more time-consuming than using specialized addressing hardware to do the work.
Support for bit manipulation includes a variety of bit-shifting operations useful for many audio compression algorithms and the ability to test and set bits individually.
For any application, whether DSP-oriented or not, processor selection requires consideration of such issues as processor speed, cost, ease of use, time to market, and on-chip peripherals. Choosing a DSP processor, however, requires attention to several additional factors, among which is an assessment of the processor's ability to maintain adequate accuracy during numeric computations. Two factors that affect this ability are the processor's computational format—fixed-point or floating-point—and its data word width.
The choice of a fixed- or floating-point processor is often one of the first determinations that must be made in narrowing the field of candidate processors. The decision is based in part on the application's requirements for precision and dynamic range. Floating-point processors provide higher dynamic range, because they represent numbers as a fractional value plus an exponent, rather than just as an integer or fractional value (as fixed-point processors do).
Floating-point data formats, the norm in general-purpose central processing units, are rare in DSPs; the vast majority of DSP processors designed, manufactured, and sold today are fixed-point processors. This is because fixed-point processors are cheaper and more energy efficient than their floating-point cousins. But these benefits come at the expense of software complexity.
Implementing an application using floating-point arithmetic is simpler because the programmer usually need not be concerned with issues related to numeric fidelity, such as overflow and saturation. Also, some applications simply cannot be efficiently implemented with a fixed-point processor. Here, the choice is relatively simple: the designer can use one of the very few available floating-point DSPs or possibly a general-purpose CPU. For many applications, however, it is possible to use either data format, so the question becomes one of trading off the benefits of ease of software development, which often influences time-to-market, against chip cost and power consumption.
The next factor to be weighed is the data word width necessary to implement the application. In general, wider data words translate into better numeric fidelity—but also into higher memory usage, higher chip cost, and possibly higher power consumption. In floating-point processors, no choice needs to be made: all current floating-point DSP processors use 32-bit data word sizes.
Most fixed-point processors, on the other hand, use 16-bit data words, though a few have 20- or 24-bit word widths. For applications needing high numeric fidelity, such as hi-fi audio, 16 bits is often insufficient or impractical. Thus, these applications often use a fixed-point DSP processor with a larger word width, or, if power and cost are not tightly constrained, a floating-point processor. —J.E & J.B.