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Selecting And Designing With DSP CoresReprinted from
Proceedings of the 1995 International Conference on Signal
Processing Applications and Technology, October 1995. Copyright © 1995 Berkeley Design Technology, Inc.
Contents1. IntroductionA DSP core is a DSP processor designed to be used as a a building-block in a custom or semi-custom integrated circuit. (Note, however, that some DSP cores are also available as off-the-shelf, packaged processors.) Using a DSP core as part of a ASIC (application specific integrated circuit) or ASSP (application specific standard product) offers opportunities for much higher integration than is possible with the use of off-the-shelf, packaged DSP processors. This higher integration in turn can yield smaller products that consume lower power, are less costly to produce, and are more resistant to reverse-engineering. However, these compelling benefits of DSP core-based design are offset by the formidable complexity of choosing and designing with DSP cores. In the past two years, there has been a dramatic increase in the number of vendors offering DSP cores and the variety of DSP cores being offered. In this paper, we describe the important characteristics of DSP cores, explain the key factors distinguishing among current commercial core offerings, and explore the design processes and tools available for creating DSP core-based ICs. A key factor determining how a DSP core can be used is whether the core is licensable or foundry-captive. A licensable core is provided to the user for use in chips which are to be fabricated in the facility of the user's choice (often this is the user's own fabrication facility). Licensable cores are generally provided by small and medium-sized companies that do not have their own chip fabrication facilities. Current vendors of licensable cores include DSP Group, Clarkspur Design, and Tensleep Design. A foundry-captive core is one that can be used only in chips that are fabricated in the vendor's own fabrication facilities. Foundry-captive cores are currently offered by Texas Instruments, AT&T Microelectronics, and SGS-Thomson Microelectronics. Note that some semiconductor vendors license a core and use it to provide foundry-captive DSP core-based ASIC services to their customers. Examples of companies who follow this approach include LSI Logic and VLSI Technology. In such cases, there are two views of the design process-to the semiconductor vendor, the design process is that of using a licensable core; to the customer (the ASIC designer), the process is that associated with a foundry-captive core. Most DSP cores today are 16-bit fixed-point architectures. Despite this commonality, the architectures of these cores vary significantly. For example, Clarkspur Design's CD2450 is a very simple, compact architecture, suitable for low-cost, moderate-performance applications. In contrast, DSP Group, Texas Instruments, and SGS-Thomson offer more elaborate architecture comparable to those of current-generation DSPs like the TMS320C5x. Several vendors offer "clone" architectures that are partially or mostly compatible with Texas Instruments' TMS320C2x or TMS320C5x processors. In some cases, the core may include memory and peripherals. In other cases, the core includes only the processor itself; memory and peripherals are added as needed, as part of the ASIC hardware external to the core. The core vendor or foundry should provide a set of macrocells which allow the ASIC designer to easily add processor-related features to the ASIC. Such functions might include parameterized memories, a memory controller, an interrupt controller, a host port, and a serial port, for example. For example, SGS-Thomson's selection of macrocells for use with their D950-CORE is particularly extensive. It is preferable that such functions be provided in the form of macrocells rather than built-in to the core, since having them as macrocells allows them to be easily omitted if they are not needed in a particular ASIC. Clarkspur Design's CD2450 carries the concept of modularity furthest-the CD2450 has a variable data word width; the ASIC designer can select a word width between 16 and 24 bits to best meet the needs of the application. Production cost, execution performance, and power consumption are important parameters for comparing DSP cores. For foundry-captive cores, these attributes are easily measured. In contrast, when using a licensable core, it is often necessary to adapt the core design to the targeted IC fabrication process. This impacts cost, performance, and power-consumption, and can make them difficult to predict. Since production cost of an integrated circuit depends heavily on its silicon area, the production cost of a DSP core is most often measured in terms of its silicon area. Silicon area measurements for common DSP cores typically range from 4 to 10 square millimeters. In addition to the cost of producing silicon, vendors of licensable cores may require royalty payments based on the number of chips produced. Since DSP cores vary significantly in the power of their instruction sets, it is important not to rely on MIPS (millions of instructions per second) ratings to compare processor performance. A better approach is to use a realistic set of benchmark functions implemented consistently across all processors and cores. Such a benchmarking effort has been undertaken by Berkeley Design Technology, and is described in detail in [1]. The results of this benchmarking show that when carefully implemented, DSP cores can achieve execution performance levels close to those of the fastest off-the-shelf DSPs. In addition, the designer of a DSP core-based ASIC can add application-specific coprocessors to supplement the DSP core and improve performance. Power consumption is a vital consideration in many DSP core applications, since many of these applications are battery-powered products. DSP core-based ASICs can consume significantly less power than equivalent printed-circuit-board-based designs, since signals that remain on-chip drive significantly smaller loads than signals that travel off-chip. As with execution speed, power consumption can only be accurately compared via a consistent benchmarking process. Unfortunately, such benchmarking is difficult to implement, since it is often impossible to differentiate between power consumed by the core and power consumed by other on-chip circuitry such as memories. As with silicon area, when using a licensable core, the execution speed and power consumption depend on how the core is adapted to the targeted fabrication process. A careful adaptation or a high-performance fabrication process will improve performance, while a straightforward implementation or a sluggish fabrication process will degrade performance. For cost-sensitive applications, designers may also want to evaluate a core's memory usage efficiency in addition to its inherent manufacturing cost. The design of a DSP core-based ASIC encompasses software and hardware design and requires a tight coupling between the two. A DSP core-based ASIC can be accurately thought of as a DSP processor-based system integrated onto a single chip. Most core vendors provide a development chip-a chip containing the core, memory, and perhaps a few peripherals. Such a chip can be used to prototype hardware and software designs before committing to custom silicon. These development chips are not produced in high volumes. Texas Instruments is unique in that their DSP cores are also available within off-the-shelf processors that are produced in volume. This allows system developers to initially design at the printed-circuit-board level, and then migrate to a DSP core-based ASIC when production volumes warrant it.
If a licensable core is being used, then the core must be adapted for use with the licensee's preferred chip design tools, or the licensee must adopt the tools supported by the core vendor. If a foundry-captive core is used, then the chip design tools supported by the foundry must be used by the ASIC designer. Licensable core designs are provided in two primary forms-full-custom, physical layout designs targeted at a particular fabrication process, and register-transfer-level descriptions written in a hardware description language (which can be used with logic synthesis tools). Some vendors provide only one of these forms, while others provide both forms. If a full-custom, physical design is provided, it will be targeted to a particular fabrication process, and modifications are usually required to make it compatible with the licensee's chosen fabrication process. These modifications to the physical design may be carried out by the core vendor or by the licensee. To facilitate modification by the licensee, the core should be provided in the form of a netlist and physical layout designs for the individual building-block cells. In addition, test vectors for verifying the modified layout should be provided, along with information needed for timing analysis. A behavioral model of the core, accurate to one clock cycle, is not strictly necessary but is an extremely valuable tool for verifying and debugging a new embodiment of the core. Some core vendors (such as DSP Group) provide a register-transfer-level description of the core in a hardware description language. This description can be processed by logic synthesis tools to create a standard-cell or gate-array implementation of the core. To create a compact, fast, and power-efficient core implementation using logic synthesis tools, the foundry must provide optimized macrocells to implement critical elements such as multipliers and memories. Once the core has been mapped into the selected fabrication process (whether by full-custom layout techniques or via logic synthesis), its functionality and timing must be verified. If errors are detected, the design is updated accordingly. When the core design is satisfactory, it undergoes a characterization process. In this process, a bounding-box specification for the core is created. The bounding-box specification captures key attributes of the core's physical and electrical design which are needed to combine the core with other components and assemble a complete chip. Typically, this information is provided in several different forms. It is provided in written form for the use of the ASIC designer and in machine-readable forms for various ASIC hardware tools. For example, physical characteristics (such as dimensions and terminal locations) are needed by placement-and-routing tools. Electrical characteristics (such as input capacitances and output drive capacities) are needed by placement-and-routing and Once a complete bounding-box specification has been created for the core, the core can be combined with other building-block components to create the complete ASIC. From this point on, the design process and tools are very similar to those for ASICs based on foundry-captive cores, discussed below. With foundry-captive cores, the foundry specifies the design methodologies and tools that are supported for the design of a core-based ASIC. Foundries may support the use of full-custom, standard cell, and/or gate array layout design styles. Depending on the customer's design expertise, resources, and preferences, the foundry may do all of the detailed design work, based on requirements and specifications provided by the customer. Typically, the foundry charges a significant fee for this engineering work. Alternatively, the customer's own designers may do most of the detailed design work, leaving only the final placement-and-routing and verification steps to the foundry. The key difference in the design of ASICs using foundry-captive cores versus those using licensable cores is that with foundry-captive cores, the internal design details and layout of the core are not revealed. Instead, the foundry provides a bounding-box specification. in addition to the bounding-box and library of compatible macrocells, the core vendor should provide a full-functional simulation model for the core. A full-functional simulation model is a model that accurately models both the internal instruction set architecture of the core processor and the external I/O interfaces. Such a model is needed for the ASIC designer to simulate the operation of the complete chip. Such a model is less critical for licensable core designs where the complete, detailed design of the core is provided (from which a gate-level simulation model can be created). For foundry-captive cores a full-functional simulation model is very important. Not all core vendors provide such models. Those that do not provide such models encourage designers to use development chips to prototype and debug a design at the board level before developing an ASIC. With this approach, the designer typically uses FPGAs to emulate the functions of ASIC hardware outside of the core. The software design process for DSP core-based ASICs, and the tools needed to support it, are quite similar to those needed for conventional, board-level, DSP processor-based system design. The key difference is that the interactions of software and hardware must be meticulously validated before the ASIC is fabricated, since post-fabrication changes to the ASIC design require a re-spin of the ASIC and are costly and time-consuming. A full-functional simulation model is important for validating hardware-software interactions. In addition, the core vendor should provide an assembler, linker, instruction set simulator, and debugger. A high-level language compiler may also be useful, but since most core-based ASICs are used in cost-sensitive applications, it is unlikely that the code size and speed penalty associated with using a high-level language would be acceptable. Ideally, the core vendor will provide an extensive set of function and application software libraries to facilitate the creation of application software on the DSP. In practice, core vendors provide widely varying levels of software support. Some vendors provide no libraries whatsoever. Others offer a smattering of function and application libraries. In the cases of the most widely-used cores, numerous third-party vendors offer extensive function and application libraries under license. DSP-based ASICs combine the performance and low cost of custom hardware with the flexibility of standard DSPs. For many high-volume applications, this is an unbeatable combination. Core-based designs are just now beginning to blossom, in large part due to a confluence of IC fabrication technology, a critical mass of industry design expertise, and improved design tools. By the end of the decade, a large percentage of high-volume embedded systems that use signal processing will be based on DSP core technology. This will benefit core vendors, ASIC vendors, and, of course, designers incorporating cores into their chips. However, designers will be faced with a wide array of core choices, and selecting among them can be a difficult task. Furthermore, designing a complex system-on-a-chip raises new difficulties for designers and design tools. In this paper, we have attempted to illuminate some of the critical issues involved in choosing and designing with DSP cores. [1] Buyer's Guide to DSP Processors, Berkeley Design Technology, Inc. (Berkeley, California), 1995. [2] DSP Design Tools and Methodologies, Berkeley Design Technology, Inc. (Berkeley, California), 1995. [3] Phil Lapsley and Jeff Bier, "DSP Cores Bring New Levels of Integration," Microprocessor Report, August 1, 1994. |
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