Audio Compression Algorithm Implementations:
Clock Rate and Memory Requirements

Berkeley Design Technology, Inc. (BDTI) provides independent analysis of digital signal processing technology
and DSP software development services. BDTI has extensive experience in the development of digital audio
products. For more information about BDTI, please visit our home page, www.BDTI.com.

As a service to the DSP community, BDTI is collecting and publishing information on optimized software
implementations of digital audio compression (and decompression) algorithms. This information is
summarized in the table below.

This information was originally assembled for use in BDTI's training class,
Digital Audio: Applications, Algorithms and Implementation.

If you have created (or know of) an optimized implementation of a digital audio compression algorithm that
isn't listed in the table below, please send it to us for inclusion in this table.
Click here for instructions on submitting information on implementations that aren't included below.

If you have corrections to, or questions about, the information on this page, please send email to
audiocomp@bdti.com.

The following table provides a brief summary of processor resource use data (clock rate, memory use) for specific
implementations of various audio compression algorithms. The clock rate listed in the table is what is actually
required by the algorithm, and is generally less than the maximum for the processor. Similarly, the memory
requirements listed are those that are actually required by the algorithm, and may in some cases exceed the
on-chip resources. The table attempts to provide separate program, constant data, and non-constant data memory
usage; where separate data was not available the table lists only total memory usage. It is assumed that
the resource requirements of each algorithm reflect the resources required to support the maximum standard
sample rate; however, sources that did not explicitly state a sample rate have no entry in the table for that column.

The sources for this data are listed in the right-hand column.

 

Algorithm	Encode/ Decode	Channels	Max Sample Rate	Chip	Clock Rate1	Memory				Link to Source
						Program	Constant Data	Non-Constant Data	Total
MPEG-1/2 Layer 1, 2	Encode	2	48 KHz	ADSP-218x	31 MHz	14Kx24-bit2		14Kx16-bit2	70 Kbyte	analog.com
				TMS320C31	18 MHz				32Kx32-bit(1K-int.+31K-ext.)	aspi.com
				TMS320C32	16 MHz				23Kx32-bit(512-int.+22.3K-ext.)	aspi.com
MPEG-1/2 Layer 1, 2	Decode	2	48 KHz	TMS320C3x	11.7 MHz	2330x32-bit	946x32-bit	705x32-bit (internal) 1612x32-bit (external)	22.4 Kbyte	ensigma.com
			48 KHz	ADSP-218x	17 MHz	14Kx24-bit2		14Kx16-bit2	70 Kbyte	analog.com
			48 KHz	TEAKLITE/ OAK core	11.94 MHz	4Kx16-bit	1558x16-bit	3434x16-bit	9Kx16-bit	ensigma.com
MP3	Decode	2		StrongARM ARM9TMDI ARM7TDMI	20 MHz 25 MHz 29 MHz				48 Kbyte3	arm.com
				DSP56303	20 MHz				8Kx24-bit internal + 48Kx24-bit external- layer II included	motorola.html
				DSP56307 /311/309/362	20 MHz				No external- layer II not included	motorola.html
			48 kHz	TEAKLITE/ OAK core	30 MHz	10Kx16-bit	6Kx16-bit	11Kx16-bit	27Kx16-bit	ensigma.com
AC-3 5.1	Decode	6		ADSP-21061	25 MHz	8Kx48-bit		19Kx32-bit	124 Kbyte	analog.com
				StrongARM4	43 MHz5 or 55 MHz6				56 Kbyte	arm.com
				ARM9TDMI4	48 MHz5 or 60 MHz6				56 Kbyte	arm.com
				Oak7	39.5 MHz	9Kx16-bit	5.5Kx16-bit	10Kx16-bit	49 Kbyte	ensigma.com
DTS				ADSP-21061	38 MHz	14Kx48-bit		62Kx32-bit	332 Kbyte	analog.com

Notes:

1. Clock rate here refers to the inverse of the instruction cycle time. Instruction cycle time
   refers to the minimum time between execution of sequential instructions (ignoring instuctions
   that execute in parallel, e.g., on superscalar or VLIW processors). Instruction cycle time does not refer
   to the latency of a single instruction, nor necessarily to the master clock cycle time, which may be some
   fraction of instruction cycle time. For example, the Motorola DSP568xx typically completes one instruction
   in two master clock cycles. This relationship, called a 2X master clock, represents the maximum rate at
   which instructions complete execution relative to the master clock rate; thus, an instruction cycle
   for the DSP568xx equals two master clock cycles. Conventional DSP architectures generally have an IPC
   (Instructions Per "Instruction" Cycle) equal to one; in such cases, there is one-to one correspondence
   between clock rate, as interpreted above, and MIPS.
2. Both encoder and decoder are included in memory allocation.
3. Requires single-cycle memory.
4. Pending certification from Dolby Laboratories.
5. Using zero wait-state, 32-bit wide SRAM.
6. Using 60ns EDO DRAM.
7. Class C.